Native and Offload Programming Models

Compiler Methodology for Intel® MIC Architecture

 

Native and Offload Programming Models

Overview

This chapter details the various programming models available on the Intel® MIC Architecture. These include the Native programming model, the Heterogeneous Offload model, and the Cilk_Offoad model. Because of the high overhead associated with data movement to/from the Intel® Xeon Phi™ coprocessor, this chapter also covers concepts in data movement and transfer and how to manage data offload.

Note that OpenMP 4.0 includes new directives for offloading execution to attached devices. The Intel Compiler supports the following OpenMP 4.0 features in the latest releases:

Goals

It is important to understand the three programming models ( Native, Offload, Cilk_Offload ) for the Intel® Xeon Phi™ coprocessor to determine which is the best match for your application. As part of this understanding and analysis, you need to understand the overheads associated with data movement and how to avoid unnecessary data movement and how to get peak transfer rates.

Topics

Goals for this chapter are to explore the offload models and data movement topics to determine which may be useful for your application:

  • How to Achieve Peak Transfer Rate (covers data movement optimization) (C++,  Fortran)

  • Techniques to Reduce Offload-related Memory Allocation Overheads (C++, Fortran)

  • Taking Advantage of Offload Pointer Association and alloc/into Keywords (C++, Fortran)

NEXT STEPS

It is essential that you read this guide from start to finish using the built-in hyperlinks to guide you along a path to a successful port and tuning of your application(s) on Intel® Xeon Phi™ coprocessors. The paths provided in this guide reflect the steps necessary to get best possible application performance.

Back to the Index for Compiler Methodology for Intel® MIC Architecture

Para obtener más información sobre las optimizaciones del compilador, consulte el aviso sobre la optimización.