Blogs del autor

Knights Corner micro-architecture support
Por James Reinders (Intel) Publicado en 05/06/12 26
How does a high performance SMP on-a-chip sound to you?  I can now share, for the first time, key details about our vision for Knights Corner (the aforementioned high performance SMP on-a-chip), and our thinking behind the software architecture and features.   There is a lot to cover here so I’ll...
TACC symposium and programming two SMP-on-a-chip devices
Por James Reinders (Intel) Publicado en 26/04/12 0
Real results for many-core processors illustrate the power of a familiar configuration (SMP) even when reduced to a single chip. SMP on-a-chip can use the same applications, same tools, offer the same flexibility and pose familiar challenges that are solved by familiar techniques and skills. I re...
Wellington and Austin: programming lots of cores
Por James Reinders (Intel) Publicado en 03/04/12 0
A couple of back-to-back opportunities to see great talks about harness lots of cores, and to give talks about programming options and why we do not need to give up on programmability in our quest for high performance.Wellington this week, Austin next week. Programming is not easy, and neither is...
Coarse-grained locks and Transactional Synchronization explained
Por James Reinders (Intel) Publicado en 07/02/12 3
Coarse-grained locks, and the importance of transactions, are key concepts that motivate why Intel Transactional Synchronization Extensions (TSX) is useful.  I’ll do my best to explain them in this blog. In my blog "Transactional Synchronization in Haswell," I describe new instructions (Intel TS...
Transactional Synchronization in Haswell
Por James Reinders (Intel) Publicado en 07/02/12 12
We have released details of Intel® Transactional Synchronization Extensions (TSX) for the future multicore processor code-named “Haswell”. The updated specification (Intel® Architecture Instruction Set Extensions Programming Reference) can be downloaded. In this blog, I’ll introduce Intel TSX and...
OPEN CASCADE introduced parallelism into SALOME SMESH Module (using our tools)
Por James Reinders (Intel) Publicado en 21/12/11 0
OPEN CASCADE S.A.S and Intel Corporation software teams decided to join their efforts to introduce parallel calculations into Salome SMESH Module. They developed with the help of Intel® Parallel Studio XE. They wrote an article about it which can be downloaded (for free) from Parallelism_in_SMESH...
"Award Winning" Intel Parallel Studio XE
Por James Reinders (Intel) Publicado en 23/11/11 5
Intel Parallel Studio XE, in the category of "Best HPC software product or technology," was honored in the annual HPCwire Readers Choice Awards. The awards are an annual feature of the publication and constitute prestigious recognition from the high performance computing community. The awards wer...
quick chat about MIC architecture with Mike Dewar, NAG
Por James Reinders (Intel) Publicado en 17/11/11 3
I ran into Mike Dewar at SC11 today as the exhibition draws to a close.  Mike is the CTO of NAG Ltd. - a company we've had the good fortune to work with for years. NAG is one of a handful of companies that have been providing feedback on our Knights Ferry (prototype MIC architecture). Mike told m...
Seeing One TeraFlop/sec, the software side, and feeling a bit emotional
Por James Reinders (Intel) Publicado en 17/11/11 0
I've known this day was coming - but when I saw Knights Corner clearly sustaining a TeraFlop (DGEMM, wide range of block sizes) per second - I was surprised by my emotional reaction inside. Hard to describe; it was a good feeling. Tuesday November 15, 2011, we showed a Knights Corner co-processor...
Ready for 2X Moore's Law: Intel Cluster Studio XE
Por James Reinders (Intel) Publicado en 08/11/11 0
Today we introduced Intel® Cluster Studio XE, an exciting collection of powerful tools, for HPC programmers who use MPI along with other programming models to make the most of clusters and supercomputers. Intel Cluster Studio XE provides two substantial new capabilities to assist in hybrid progra...