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Courseware - Parallel Computation

  • Overview of topics
  • Models of computation
  • Kinds of computation
  • Task parallelism
  • Data parallelism
  • Event parallelism
  • Properties of computation
  • Bandwidth
  • Latency
  • Scalability
  • Granularity
  • Parallel architectures
  • Processor architectures including multi-core
  • Memory systems for high performance
  • Caching and coherence
  • Clusters
  • Parallel programming paradigms
  • Threading
  • Message passing
  • Event driven techniques
  • Parallel software architectures
  • MapReduce
  • Grid computing
  • Open community distributed computing (BOINC, SETI, …)
  • Parallel fault simulation algorithm for multi-core systems with common memory
  • Material Type:

    Article / White paper

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    Technical Format:

    PDF document

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    Date Added:

    08/26/2010

    Date Modified:

    08/26/2010

    Author

    Dr. Dmitry E. Ivanov, Institute of Applied Mathematics and Mechanics NAS of Ukraine
    Description:

    Fault simulation for sequential circuits numbers among the highly compute-intensive tasks in the integrated circuit design process. In this paper we propose a new parallel fault simulation algorithm for multi-core workstations with common memory. We use dynamic fault grouping for each input test vector. Also each formed group is simulated in separate thread. Also we study the scalability of proposed algorithm. We report results for the ISCAS-89 benchmark circuits obtained on Intel’s MTL with 12 computational cores.

    Recommended Audience:

    Advanced programmers, Graduate students

    Language:

    Russian

    Keywords:

    sequential, circuit, fault, simulation, parallel, programming, manycore, computational, system
  • Scalable parallel genetic algorithm for identifying sequences construction
  • Material Type:

    Article / White paper

    ISN Logo

    Technical Format:

    PDF document

    URL:

    Go to URL

    Location:

    Go to materials

    Date Added:

    08/26/2010

    Date Modified:

    08/26/2010

    Author

    Dr. Dmitry E. Ivanov, Institute of Applied Mathematics and Mechanics NAS of Ukraine
    Description:

    The task of constructing of identifying sequences for synchronous sequential circuits is one of the central problems in the design process. Genetic algorithm (GA) is one of the possible solutions of this task. It uses simulation of digital circuits to value the quality of potential solutions. Due this fact GA of input sequences generation are very slowly. In this paper we propose parallel versions of GA of this type that adapted for multi-core workstations. In our approach we organize several parallel threads. Each thread evaluates fitness-function for own individual by simulating circuit’s behavior. This schema is known as «master-slave». We also study the scalability of this type parallel GA on systems with large numbers of computational cores. We present results for circuits in the ISCAS-89 benchmark set obtained on the Intel’s MTL with 12 cores.

    Recommended Audience:

    Advanced programmers, Graduate students

    Language:

    Russian

    Keywords:

    genetic, algorithm, sequential, circuits, simulation, manycore, computational, system, parallel, programming