The task of constructing of identifying sequences for synchronous sequential circuits is one of the central problems in the design process. Genetic algorithm (GA) is one of the possible solutions of this task. It uses simulation of digital circuits to value the quality of potential solutions. Due this fact GA of input sequences generation are very slowly. In this paper we propose parallel versions of GA of this type that adapted for multi-core workstations. In our approach we organize several parallel threads. Each thread evaluates fitness-function for own individual by simulating circuit’s behavior. This schema is known as «master-slave». We also study the scalability of this type parallel GA on systems with large numbers of computational cores. We present results for circuits in the ISCAS-89 benchmark set obtained on the Intel’s MTL with 12 cores.
Para obtener más información sobre las optimizaciones del compilador, consulte el aviso sobre la optimización.