Logical Operators

The logical operators use the symbols and intrinsics listed in the following table.

Bitwise Operation

Operator Symbols Syntax Usage

Corresponding Intrinsic

Standard

w/assign

Standard

w/assign

AND

&

&=

R = A & B

R &= A

_mm_and_si64
_mm_and_si128

OR

|

|=

R = A | B

R |= A

_mm_and_si64
_mm_and_si128

XOR

^

^=

R = A^B

R ^= A

_mm_and_si64
_mm_and_si128

ANDNOT

andnot

N/A

R = A andnot B

N/A

_mm_and_si64
_mm_and_si128

Logical Operators and Miscellaneous Exceptions

A and B converted to M64. Result assigned to Iu8vec8.

I64vec1 A;

Is8vec8 B;

Iu8vec8 C;

C = A & B;

Same size and signedness operators return the nearest common ancestor.

I32vec2 R = Is32vec2 A ^ Iu32vec2 B;

A&B returns M64, which is cast to Iu8vec8.

C = Iu8vec8(A&B)+ C;

When A and B are of the same class, they return the same type. When A and B are of different classes, the return value is the return type of the nearest common ancestor.

The logical operator returns values for combinations of classes, listed in the following tables, apply when A and B are of different classes.

Ivec Logical Operator Overloading

Return (R)

AND

OR

XOR

NAND

A Operand

B Operand

I64vec1 R

&

|

^

andnot

I[s|u]64vec2 A

I[s|u]64vec2 B

I64vec2 R

&

|

^

andnot

I[s|u]64vec2 A

I[s|u]64vec2 B

I32vec2 R

&

|

^

andnot

I[s|u]32vec2 A

I[s|u]32vec2 B

I32vec4 R

&

|

^

andnot

I[s|u]32vec4 A

I[s|u]32vec4 B

I16vec4 R

&

|

^

andnot

I[s|u]16vec4 A

I[s|u]16vec4 B

I16vec8 R

&

|

^

andnot

I[s|u]16vec8 A

I[s|u]16vec8 B

I8vec8 R

&

|

^

andnot

I[s|u]8vec8 A

I[s|u]8vec8 B

I8vec16 R

&

|

^

andnot

I[s|u]8vec16 A

I[s|u]8vec16 B

For logical operators with assignment, the return value of R is always the same data type as the pre-declared value of R as listed in the table that follows.

Ivec Logical Operator Overloading with Assignment

Return Type

Left Side (R)

AND

OR

XOR

Right Side (Any Ivec Type)

I128vec1

I128vec1 R

&=

|=

^=

I[s|u][N]vec[N] A;

I64vec1

I64vec1 R

&=

|=

^=

I[s|u][N]vec[N] A;

I64vec2

I64vec2 R

&=

|=

^=

I[s|u][N]vec[N] A;

I[x]32vec4

I[x]32vec4 R

&=

|=

^=

I[s|u][N]vec[N] A;

I[x]32vec2

I[x]32vec2 R

&=

|=

^=

I[s|u][N]vec[N] A;

I[x]16vec8

I[x]16vec8 R

&=

|=

^=

I[s|u][N]vec[N] A;

I[x]16vec4

I[x]16vec4 R

&=

|=

^=

I[s|u][N]vec[N] A;

I[x]8vec16

I[x]8vec16 R

&=

|=

^=

I[s|u][N]vec[N] A;

I[x]8vec8

I[x]8vec8 R

&=

|=

^=

I[s|u][N]vec[N] A;

Para obtener información más completa sobre las optimizaciones del compilador, consulte nuestro Aviso de optimización.