_mm256_srlv_epi32/64

Logical shift of doubleword/quadword elements to right according variable values. The corresponding Intel® AVX2 instruction is VPSRLVD or VPSRLVQ.

Syntax

extern __m256i _mm256_srlv_epi32(__m256i s1, __m256i s2);

extern __m256i _mm256_srlv_epi64(__m256i s1, __m256i s2);

Arguments

s1

integer source vector used for the operation

s2

integer source vector providing variable values for shift operation

Description

Performs a logical shift of 32 or 64 bits (doublewords, or quadword) in the individual data elements in source vector s1 to the right by the count value of corresponding data elements in source vector s2. As the bits in the data elements are shifted right, the empty low-order bits are cleared (set to '0').

The count values are specified individually in each data element of the second source vector. If the unsigned integer value specified in the respective data element of the second source vector is greater than 31 (for a doubleword), or 63 (for a quadword), then the destination data elements are set to '0'.

Returns

Result of the right-shift operation.

Para obtener información más completa sobre las optimizaciones del compilador, consulte nuestro Aviso de optimización.