Zona para desarrolladores Intel®:
Intel ISA Extensions

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Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Tema / Iniciador del tema Fecha del envío Respuestas Último envíoordenar ascendente
Tema controversial Siempre arriba: Links to instruction documentation
por Thomas Willhalm...
Vie, 31/12/2010 - 07:07 35
por james l.
Dom, 19/03/2017 - 15:43
Tema controversial Siempre arriba: Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
por Roman Dementiev...
Vie, 07/06/2013 - 06:46 6
por D. Hugh R.
Sáb, 21/05/2016 - 09:28
Tema controversial Siempre arriba: Intel® Software Development Emulator release 7.30
por Mark Charney (Intel)
Lun, 21/09/2015 - 05:23 3
por Sergio J. C.
Mié, 16/12/2015 - 12:26
Tema regular could not decode some pattern of vgatherdps
por mitsunari s.
Jue, 13/09/2018 - 22:41 4
por mitsunari s.
Vie, 21/09/2018 - 05:48
Tema popular Disabling HW prefetcher
por Intel C.
Sáb, 25/08/2018 - 03:02 33
por McCalpin, John
Mié, 19/09/2018 - 08:30
Tema regular MWAIT is not improving performance and why my machine stucks?
por Zihan Y.
Vie, 03/08/2018 - 02:14 3
por alex, henry
Mar, 18/09/2018 - 14:18
Tema regular Determining wake up reason for MWAIT
por AG, Phillip
Jue, 13/09/2018 - 02:21 1
por Cownie, James H...
Vie, 14/09/2018 - 01:44
Tema popular Bugs in Intrinsics Guide (Page: 1, 2, 3, 4)
por andysem
Mié, 30/01/2013 - 00:24 171
por Eden S. (Intel)
Lun, 10/09/2018 - 03:49
Tema regular Intrinsic functions _rdtsc and _rdtscp
por Intel C.
Lun, 13/08/2018 - 10:56 12
por McCalpin, John
Mar, 28/08/2018 - 17:07
Tema popular Intel® Xeon Phi™ x200 series (KNL) Ring 3 Monitor/MWait
por Cownie, James H...
Jue, 13/10/2016 - 02:04 20
por Zihan Y.
Mié, 08/08/2018 - 19:17
Tema regular When will SnowRidge be available?
por Zihan Y.
Dom, 22/07/2018 - 19:16 2
por Zihan Y.
Mar, 24/07/2018 - 06:30
Tema regular RDTSC to measure performance of small # of FP calculations
por Drum, Anthony
Vie, 20/07/2018 - 03:48 2
por Drum, Anthony
Lun, 23/07/2018 - 08:25
Tema regular I understand Why SSE is slower than ANSI C
por Yavorski, Nick
Jue, 19/07/2018 - 03:52 0
por Yavorski, Nick
Jue, 19/07/2018 - 03:52
Tema regular Using AVX opcodes slow my proc
por Dmk Z.
Vie, 08/06/2018 - 08:34 2
por Dmk Z.
Vie, 13/07/2018 - 07:53
Tema regular State of AVX 512 on Skylake-X
por jan v.
Sáb, 08/07/2017 - 02:17 10
por jan v.
Mar, 03/07/2018 - 08:54
Tema regular Error in pseudo-code for RDPMC in SWDM Volume 2
por McCalpin, John
Mar, 19/06/2018 - 08:33 5
por McCalpin, John
Vie, 22/06/2018 - 11:19
Tema regular what are the performance implications of using vmovups and vmovapd instructions respectively?
por Aketh T.
Mié, 20/06/2018 - 13:22 1
por McCalpin, John
Jue, 21/06/2018 - 09:20
Tema regular Confusion in behavior of _mm256_loadu_ps and _mm256_loadu_ps instrinsics
por Aketh T.
Jue, 21/06/2018 - 07:05 1
por McCalpin, John
Jue, 21/06/2018 - 09:05
Tema regular AVX-512 release date
por いらきゅ
Dom, 03/06/2018 - 21:56 4
por いらきゅ
Sáb, 16/06/2018 - 12:19
Tema regular KUNPCK* instructions behavior in SDM and Intrinsics Guide
por andysem
Jue, 14/06/2018 - 17:08 1
por Mark Charney (Intel)
Vie, 15/06/2018 - 05:31
Tema regular gcc not finding a _mm256_storeu2_m128i
por rajathadripura ...
Mié, 06/06/2018 - 07:10 1
por Richard Nutman
Vie, 08/06/2018 - 05:04
Tema regular LDDQU vs. MOVDQU guidelines
por andysem
Jue, 03/05/2018 - 09:59 9
por Travis D.
Mar, 15/05/2018 - 21:03
Tema regular The memory ordering semantics of mfence versus those of locked instructions
por Travis D.
Mié, 09/05/2018 - 20:51 1
por McCalpin, John
Jue, 10/05/2018 - 11:12
Tema regular Support for saturation and addition instruction in AVX-512
por Udupi, Nagacharan
Lun, 19/03/2018 - 12:39 1
por Christopher H.
Dom, 06/05/2018 - 01:01
Tema regular What is the status of VZEROUPPER use?
por Agner
Vie, 25/11/2016 - 12:22 12
por Agner
Lun, 23/04/2018 - 10:32
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