Zona para desarrolladores Intel®:
Intel ISA Extensions

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Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication
  • Intel® SGX forum support has been moved to a new location
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Private messages can only be initiated by Intel employees and members of the Intel® Black Belt Developer program.
Tema / Iniciador del tema Fecha del envío Respuestas Último envíoordenar ascendente
Tema controversial Siempre arriba: Links to instruction documentation
por Thomas Willhalm...
Vie, 31/12/2010 - 07:07 35
por james l.
Dom, 19/03/2017 - 15:43
Tema controversial Siempre arriba: Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
por Roman Dementiev...
Vie, 07/06/2013 - 06:46 6
por D. Hugh R.
Sáb, 21/05/2016 - 09:28
Tema controversial Siempre arriba: Intel® Software Development Emulator release 7.30
por Mark Charney (Intel)
Lun, 21/09/2015 - 05:23 3
por Sergio J. C.
Mié, 16/12/2015 - 12:26
Tema regular LDDQU vs. MOVDQU guidelines
por andysem
Jue, 03/05/2018 - 09:59 9
por Travis D.
Mar, 15/05/2018 - 21:03
Tema regular The memory ordering semantics of mfence versus those of locked instructions
por Travis D.
Mié, 09/05/2018 - 20:51 1
por McCalpin, John
Jue, 10/05/2018 - 11:12
Tema regular Support for saturation and addition instruction in AVX-512
por Udupi, Nagacharan
Lun, 19/03/2018 - 12:39 1
por Christopher H.
Dom, 06/05/2018 - 01:01
Tema regular What is the status of VZEROUPPER use?
por Agner
Vie, 25/11/2016 - 12:22 12
por Agner
Lun, 23/04/2018 - 10:32
Tema popular Bugs in Intrinsics Guide (Page: 1, 2, 3, 4)
por andysem
Mié, 30/01/2013 - 00:24 164
por Matthias Kretz
Lun, 23/04/2018 - 01:40
Tema regular Enabling Mon feature using IA32_MISC_ENABLES
por K., Sina
Lun, 09/04/2018 - 23:24 0
por K., Sina
Lun, 09/04/2018 - 23:24
Tema regular Possible errors in instruction semantics
por Dasgupta, Sandeep
Mié, 04/04/2018 - 17:48 4
por Dasgupta, Sandeep
Jue, 05/04/2018 - 13:36
Tema regular Update the SDE MSVS debugger install kit to support VS2017?
por Ens, John
Vie, 22/12/2017 - 07:40 1
por Ady Tal (Intel)
Sáb, 31/03/2018 - 23:56
Tema regular Immediate operands for SSE instructions?
por Luchezar B.
Jue, 22/03/2018 - 08:48 0
por Luchezar B.
Jue, 22/03/2018 - 08:48
Tema popular Why is Intel allowing this?!?
por Igor Levicki
Vie, 14/04/2017 - 17:01 38
por Igor Levicki
Mié, 21/03/2018 - 12:38
Tema regular Vector processing needs better NAN propagation
por Agner
Lun, 19/03/2018 - 00:41 7
por Agner
Mar, 20/03/2018 - 23:50
Tema regular Performance delays - programming with QNan and Denormals
por zalia64
Mar, 13/03/2018 - 08:12 7
por McCalpin, John
Mar, 20/03/2018 - 10:45
Tema regular How to get the FLOP number of an application?
por zhang t.
Vie, 02/03/2018 - 17:51 9
por jimdempseyatthecove
Mar, 13/03/2018 - 14:57
Tema regular Histogram examples using AVX-512 CD in Dec 2017 Optimization Ref Manual are wrong?
por Nelson, Trent
Jue, 01/03/2018 - 06:37 6
por Christopher H. ...
Sáb, 03/03/2018 - 15:41
Tema regular How to Reduce CAL (Function Call Interrupts ) on x86_64 architectures in /proc/interrupts
por Kumar, Satish
Mar, 20/02/2018 - 00:00 0
por Kumar, Satish
Mar, 20/02/2018 - 00:00
Tema regular Convert bytes to nibbles
por CommanderLake
Mar, 07/11/2017 - 07:56 3
por Igor Levicki
Mar, 13/02/2018 - 10:21
Tema regular Parallel dependence in bitmap scaling code
por CommanderLake
Sáb, 03/02/2018 - 18:55 7
por jimdempseyatthecove
Mié, 07/02/2018 - 05:26
Tema regular If the frequency is set to the P_STATE 1, why AVX-512 is not running to its base frequency?
por Jordi V.
Mar, 23/01/2018 - 12:32 3
por McCalpin, John
Jue, 25/01/2018 - 07:12
Tema regular AVX-512 VBMI2: why no vector version of _pext_u32()?
por Mikkelsen, Morten
Jue, 11/01/2018 - 16:24 0
por Mikkelsen, Morten
Jue, 11/01/2018 - 16:24
Tema regular how to turn off out-of-order execution in Intel processor
por ddmetro
Dom, 25/10/2009 - 14:32 14
por william l.
Mié, 03/01/2018 - 21:15
Tema regular AVX512-VBMI2: VPSHLDV masks its shift count preventing use as a blend
por Peter Cordes
Sáb, 09/12/2017 - 12:23 0
por Peter Cordes
Sáb, 09/12/2017 - 12:23
Tema regular AVX512 missing intrinsics
por Cloyz
Sáb, 25/11/2017 - 15:38 3
por Peter Cordes
Sáb, 09/12/2017 - 11:46
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