Papers on MIC: TACC-Intel Highly Parallel Computing Symposium

Papers on MIC: TACC-Intel Highly Parallel Computing Symposium

Imagen de James Reinders (Intel)

The "TACC-Intel Highly Parallel Computing Symposium" was held on April 10-11, 2012, in Austin, Texas.

The presentations are available at http://www.tacc.utexas.edu/ti-hpcs12/program.

This offers a diverse set of published results on the prototype systems using Intel Many Integrated Core (MIC) architecture.

I wrote some commentary a blog.

- james

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Imagen de gaston-hillar

Is MIC going to provide any AVX improvements? Can you share some info about that?Thanks for sharing the presentation.

Gastón C. Hillar

There is not yet a production AVX-512 implementation. Reconciliation of MIC instruction sets with future AVX is a publicized goal. Already the compiilers share some commonality in how they target AVX and MIC, and some of the changes announced for 13.0 compilers move in that direction.

Imagen de Georg Zitzlsberger (Intel)

Hello Gastn,

no details are yet public. However, we're planing to publish descriptions about the instruction set in some weeks. The first who announces them is James Reinders. He's got a blog and RSS feed you might subscribe to to get the information hot off the press:
http://software.intel.com/en-us/blogs/author/james-reinders/

Edit:
The "Knights Corner Instruction Set Reference Manual" is already online (I've missed that):
http://software.intel.com/en-us/forums/showthread.php?t=105443

Best regards,

Georg Zitzlsberger

Reconciliation of MIC instruction sets with future AVX is a publicized goal.

Very interesting,I hope the converged ISAwill be based onMVEX since it looks more powerful than VEX with 2x the number oflogical registers, the predication masks and swizzles/conversions

Quoting bronxzv

Reconciliation of MIC instruction sets with future AVX is a publicized goal.

Very interesting,I hope the converged ISAwill be based onMVEX since it looks more powerful than VEX with 2x the number oflogical registers, the predication masks and swizzles/conversions

I wouldn't count on it. There are inherent incompatibilities, and the only realistic option is to replace the ISA of the MIC. Hence VEX will prevail. Note that the MIC instruction set will be reconciledwith AVXn, not the other way around.

2x the registers isn't necessary for the CPU with plenty of memory ports, store-to-load forwarding, and out-of-order execution with register renaming. More architectural registers would mainly be used for hiding latency, but this can also be achieved by breaking AVX-512 instructions up into 256-bit portions at issue. Which would also save power and storage in the front-end. With AVX-512 prevailing that would mean the MIC will have to deal with having fewer registers instead, but it can compensate with 8-way SMT.

Having dedicated predication registers is not an option for the CPU. The masking adds latency to the ALUs, and the routing of these extra operands and checking for dependencies costs a lot on an out-of-order architecture. Furthermore, divergent algorithms are not suited for high performance SIMD anyway, so why pay the price of dedicated predication with algorithms that are? For the situations where predication really is useful, you can simply use the blend instructions.

the only realistic option is to replace the ISA of the MIC

it doesn't lookrealistic at all (from a market acceptance POV)to replace it just afterits first public documentation was released, hint: the zmm nomenclature on MIC. Now, I'll certainly not waste time guessing anymore with the disclosure in justa few weeks http://software.intel.com/en-us/forums/showpost.php?p=190761

Quoting bronxzv

the only realistic option is to replace the ISA of the MIC

it doesn't lookrealistic at all (from a market acceptance POV)to replace it just afterits first public documentation was released, hint: the zmm nomenclature on MIC. Now, I'll certainly not waste time guessing anymore with the disclosure in justa few weeks http://software.intel.com/en-us/forums/showpost.php?p=190761

Market acceptance won't be negatively affected by the ISA change. The vast majority of code is written in a high-level language and it only requires a recompile to run it on a new device, which is something the HPC market is very familiar with.Reconciliating the ISA should even help market acceptance because you can test on a workstation and deploy the same binary on a MIC supercomputer. It also allows to easily balance the workload between CPUs and MICs, and facilitates debugging and profiling.

And I'm not sure what you're holding your breath for. The ISA has been fully disclosed.

Imagen de James Reinders (Intel)

Regarding "Now, I'll certainly not waste time guessing anymore with the disclosure in just a few weeks" http://software.intel.com/en-us/forums/showpost.php?p=190761

Nicolas is right when he says the ISA (for KNC)has been disclosed... George was behind (who posted what you pointed to)... and as he notes now in his post... the ISA document is out (the one you are debating about).

We've not committed publicly how future products will go beyond IMCI (512 bits on Knights Corner) and AVX2... we are still taking input! We are listening- so keep it coming!

Any discussion about AVX3 or beyond is speculation... enjoy it, but be careful what you read on the internet...

And I'm not sure what you're holding your breath for.

I wait for details about the "Reconciliation of MIC instruction sets with future AVX" mentioned by TimP as a "publicized" goal here http://software.intel.com/en-us/forums/showpost.php?p=190704

it should bepretty obvious that I'm fully aware of the KNC ISA disclosure since I mentioned MVEX encoding and the zmm nomenclature

Regarding "Now, I'll certainly not waste time guessing anymore with the disclosure in just a few weeks" http://software.intel.com/en-us/forums/showpost.php?p=190761

the Georg's post I was refering to waspromising some near futuredisclosure (andwas updated after my own post)thus my confusion sincethe Knights Corner ISA is public since early June, 2012

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