I was trying to count number of fluhses to TLB using performaqnce counters. One of the event that looked interesting to me is the "TLB_FLUSH.STLB_ANY" with event number BDH and mask 20H. The System Programing guide 3B (http://download.intel.com/products/processor/manual/253669.pdf) mentions that this measures "Count number of STLB flush attempts". Does this mean that this counts the number of TLB flusehes for the second level TLB? Does any body have better understanding of what this event really counts.
I am more confused by the fact that when I measure another related counter TLB_FLUSH.DTLB_THREAD (same event number but mask is 01H and supossedly counts DTLB flush attempts of the thread-specific entries), it shows a much smaller value than the measured value of TLB_FLUSH.STLB_ANY. I am not understanding under what circumstances the L1 DTLB will not be flushed but STLB will be flushed. I should be missing something. Can somebody help me out here? Any body has an idea how these are related too writes to CR3 and/or CR4 registers?