MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS opcode for sandy bridge?

MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS opcode for sandy bridge?

Hi!

I'm working on the FreeBSD hwpmc support for Sandy Bridge. A lot of the tuning whitepapers and forum posts for Sandy Bridge mention MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS_PS but I can't find it in the SDM. What's the PMC MSR event ID and unit mask for this event?

Thanks!

-adrian

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Hello Adrian,

From https://github.com/andikleen/pmu-tools/blob/master/snb-client.csv it looks like the event code is 0xd4 and umask 0x02.

Pat

Hi!

Ok, thanks!

Next from that guide is this - MEM_LOAD_RETIRED.L3_HIT_PS. The entire formula is:

% of cycles spent on last level cache access (2nd level misses that hit in LLC):
((MEM_LOAD_RETIRED.L3_HIT_PS * 26) + (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS
* 43) +
(MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS * 60)) / CPU_CLK_UNHALTED.THREAD

(The slide set is: http://download-software.intel.com/sites/landingpage/legacy/pdfs/Using_I...)

Thanks!

-adrian

Is there a question?

Pat

Ah, yes. I can't seem to find the opcode/mask for MEM_LOAD_RETIRED.L3_HIT_PS . Would you be able to help me figure out what that actually refers to?

Thanks!

-adrian

Yeah... sorry... I figured that out right after I sent my reply. It is the same opcode/mask as the event without _PS. The _PS means it is a precise event so you need to do the programming for precise events.

Pat

Hm, so D1/04 ?

-adrian

Yes... probably 0xd1/0x04 as you suggest. It also might be D2/01. I will have to ask the person who tries to keep track of event renaming and get back to you.

Pat

Thanks!

Is "special" here "PEBS" ? Can I ignore programming the PEBS bits if I don't care about the events themselves and just want counter / sample triggers?

Thanks!

-adrian

Hello Adrian,

Yes you can ignore (not program) the PEBS stuff if you don't want it and just use the event as if it is a not-PEBS event.

Pat

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