I'm tring to calculate the L2 miss ratio of a program on the platform of Intel Core2 michroarchitecture.
I'm using the the formula : L2 miss ratio = L2_LINE_IN.SELF.ANY / L2_RQST.BOTH_CORES.ANY_MESI .
However, the results really confused me that L2_RQST.BOTH_CORES.ANY_MESI=0, while L2_RQST.BOTH_CORES.ANY_MESI > 0.
It happens under the situation that the input is smaller and the program runs a very short time.
If there are no requests to L2, where do the misses come from ?
I check the Vtune manual and I think L2_LINE_IN.SELF.ANY means the all the L2 cache line misses including the instruction prefetch,
And L2_RQST.BOTH_CORES.ANY_MESI means all completed L2 cache requests when BOTH_CORES counts events initiated by either core, ANY counts demand requests and requests from the L2 hardware prefetchers and MESI counts how many times cache lines in any state are accessed.
Am I take the 2 events in a wrong way?
Any help would be appreciated.