How can L2_RQST.BOTH_CORES.ANY_MESI=0 while L2_LINE_IN.SELF.ANY >0 ?

How can L2_RQST.BOTH_CORES.ANY_MESI=0 while L2_LINE_IN.SELF.ANY >0 ?

Hi all~

I'm tring to calculate the L2 miss ratio of a program on the platform of Intel Core2 michroarchitecture.

I'm using the the formula : L2 miss ratio =  L2_LINE_IN.SELF.ANY / L2_RQST.BOTH_CORES.ANY_MESI .

However, the results really confused me that  L2_RQST.BOTH_CORES.ANY_MESI=0, while L2_RQST.BOTH_CORES.ANY_MESI > 0.

It happens under the situation that the input is smaller and the program runs a very short time.

If there are no requests to L2, where do the misses come from ?

I check the Vtune manual and I think L2_LINE_IN.SELF.ANY means the all the L2 cache line misses including the instruction prefetch,

And L2_RQST.BOTH_CORES.ANY_MESI means all completed L2 cache requests when BOTH_CORES counts events initiated by either core, ANY counts demand requests and requests from the L2 hardware prefetchers and MESI  counts how many times cache lines in any state are accessed.

Am I take the 2 events in a wrong way?

Any help would be appreciated.

Sun

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> I'm using the the formula : L2 miss ratio =  L2_LINE_IN.SELF.ANY / L2_RQST.BOTH_CORES.ANY_MESI .

It depends on processor's architecture, and I can't find event  L2_RQST.BOTH_CORES.ANY_MESI support  in my Ivy-Bridge processor, my opinion is to use:

L2 % miss rate = L2_LINE_IN.ANY / L2_TRANSACTIONS.ANY

Quote:

Peter Wang (Intel) wrote:

> I'm using the the formula : L2 miss ratio =  L2_LINE_IN.SELF.ANY / L2_RQST.BOTH_CORES.ANY_MESI .

It depends on processor's architecture, and I can't find event  L2_RQST.BOTH_CORES.ANY_MESI support  in my Ivy-Bridge processor, my opinion is to use:

L2 % miss rate = L2_LINE_IN.ANY / L2_TRANSACTIONS.ANY

Thanks for replying. But I think I don't make it clear here.

I know that the name of the hardware events varies on different platform.

But the problem is , from the explanations of vtune manual, I'm pretty sure that the event  L2_RQST.BOTH_CORES.ANY_MESI is all the requests to the L2  cache. However, the results turn out to be unexpected. 

If I'm right, then how could  L2_RQST.BOTH_CORES.ANY_MESI=0 while  L2_LINE_IN.SELF.ANY>0 ?

If I'm wrong, then what is the hardware event representing all the requests to the L2? Since I can't find any,other than L2_RQST.BOTH_CORES.ANY_MESI.

 

 

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