The Intel® Joule™ platform is a system on module (SoM) and is available in multiple configurations that share the same footprint and interface connector placement. This enables accelerated product design by providing multiple levels of compute power, graphics, memory and communication options in a single common footprint that can scale with end-product requirements.

Intel® Joule™ Module Configurations

There are two configurations of the module.

Module CPU Clock Graphic Clock Memory and Storage
Intel Joule 550x module 1.5 GHz 300 GHz 3GB RAM and 8GB eMMC Flash
Intel Joule 570x module 1.7 GHZ; Turbo Boost up to 2.4 GHz 450 MHz base, 650 MHz Turbo 4GB RAM and 16GB eMMC Flash

 

Intel Joule Compute Module Feature Summary

Domain Attribute Value Notes
Compute System on Chip
Address Bus Size
Cache
14mm Intel® Atom™ Processor
64-bit (x86-64)
4MB L1
Quad-core: 4 core supporting 2 threads per core
2MB per core-pair
RAM Type and speed LPDDR4 (4 lanes, 3200 MT/sec) Integrated Package on Package
Graphics Execution Units
Open Graphics Libraries
12EUs (2x6) on 550x and 18EUs on 570x
OpenGL 3.1ES, OpenGL 4.3, and OpenCL 2.0
 
Display HDMI Output HDMI 1.4b 1080p
Storage Type Supported eMMC 5.0 Max eMMC speed of 400 MB/second
MIPI CSI Camera connectors
MIPI CSI specification
Supported resolutions
 
Module accepts Hirose* BM14B(0.8)-40DP-0.4V
Two CSI2 D-PHY ports at 1.5 Gb/sec per lane
Camera1 (13MP)
Camera2 (5MP)
Data, clock, power, and GPIO on each connector
Supports two simultaneous cameras
 
 
Expansion Connector Module to expansion board Two, 2x50 pin connectors Hirose Electric Co LTD*
Part number DF40C-100DP-0.4V
Audio Number of DMICs
Number and Speed of I2S
2
One I2S at 9.6 MHz
Routed via expansion board connectors
 
USB USB 3.0 compliant 1 Type-C OTG and 1 Host USB3, Port 0 is dedicated to Type-C
USB3, Port 1 is multiplexed with PCIe
PCIe* Number of Ports/lanes
Max Speed
1 port / 1 lane
5 Gb/s
Multiplexed with USB 3, Port 1
 
SIO I2C
UARTS
 
SPI
5 ports (3 LPSS, 2 ISH as LPSS)
2 full and 1 half
 
2 ports, 5 chip selects
Master Mode; max 3.4 Mb/s
Maximum rate of 115.2 kb/s for half speed and 3.6864 Mb/s maximum for full speed modes
Up to 25 MHz
SDIO Number of ports 1 For SD Card interface
Wi-Fi* and Bluetooth® Integrated wireless module
Bands
Standards
Security
 
Dual mode, BT 4.2 Core
Intel® Dual Band Wireless - AC 8260
Dual Band MIMO 2x2
IEEE 8.02.11agn + ac, BT 4.2 core
WPA, WPA2,WPS2, 802.11w, WMM, WMM-PS,WFD, Miracast, Passpoint
Over 15 profiles supported
 
2.4 and 5 GHz
 
 
 
WPA2, AES-CCMP encryption
Antenna Dual MHF4 connectors on module Connection A1 is Wi-Fi* only while connection A2 services both BT and Wi-Fi*  
Power Manager Integrated PMIC SoC specific PMIC Not user programmable

See also: Domain Features for a different description of features.

Expansion Board Requirements

The Expansion Board Design Guide provides design recommendations for designing customer expansion boards. At a minimum, the following elements are required to enable successful module boot and operation.

Method for connecting module to expansion board

The module must be securely mounted to an expansion board in a method that maintains full engagement of the board-to-board interface connectors. See the Mechanical and Environmental topic for more information.

Method to provide +VSYS power to the module

The subject is covered in Power Delivery, Signaling and Reset.

Required strapping of module pins

These module pin strappings must be implemented for boot during rising edge of PMIC_PWRGOOD (J6, pin 33). See Power Good in Power Delivery, Signaling, and Reset for details and Boot Strap Signal Isolation for an example isolation circuit.

Signal Name Location Default Requirement
UART_0_TXD J6, pin 93 Internal 20k pull down Must be Hi-z or pulled down to GND each time PMIC_PWRGOOD asserts
ISH_UART0_RTS J7, pin 11 Internal 20k pull up Must be Hi-z or pulled up to +VDD1 each time PMIC_PWRGOOD asserts
ISH_UART0_TXD J7, pin 15 Internal 20k pull down Must be Hi-z or pulled down to GND each time PMIC_PWRGOOD asserts
SPI_0_FS1 J7, pin 79 Internal 20k pull up Must be Hi-z or pulled up to +VDD1 each time PMIC_PWRGOOD asserts
SPI_0_FS0 J7, pin 77 Internal 20k pull down Must be Hi-z or pulled down to GND each time PMIC_PWRGOOD asserts
SPI_1_FS2 J6, pin 14 Internal 20k pull up Must be Hi-z or pulled up to +VDD1 each time PMIC_PWRGOOD asserts

BIOS installed on the module

The module requires a Basic Input Output System (BIOS) code to be installed in the device firmware in order to complete the boot and initialization process. The reference configuration loaded during module production can be overwritten with either an updated, approved reference BIOS or a custom BIOS developed by other users, customers or partners.

Caution: Turning off the device during a BIOS update can cause data corruption and loss of functionality.

 

WARNING:
End-use equipment integrating the device has to be authorized as required by the U.S. Federal Communications Commission ("FCC") or it has to be operated in accordance with the FCC's rules on operation of unauthorized devices (47 C.F.R. § 2.805), including obtaining approval from any licensed spectrum operator, if the end-use equipment will use such operator's spectrum.

See also Regulatory information for the Intel® Joule™ Compute Module.

Expansion Board Recommendations

Power button

Connect an active low power button to J6 pin 9 to trigger a reset or to power cycle the board.

DnX button

Connect an active high (VDD1) signal to J6, pin 78 to initiate a Download and Execute routine that will update the BIOS via USB 2.0, port 0. This DnX button signal is the only way to initiate the Download and Execute update process.

Real time clock (RTC) backup power source

See the Clock Specifications section.

UART debugging

Include a method to access UART port 2 on the module during boot to collect debug information as this is the only way to access debug messages generated during the power on and boot sequences.

Optional - External EEPROM

An external EEPROM can be connected to I2C port 0 to hold a specific configuration of the multipurpose pins. Intel® does not provide a tool to populate the EEPROM device. If you decide to use an EEPROM device, consider an ST Microelectronics M24M02-DR* or equivalent. During boot, if the BIOS does not find an EEPROM device attached to I2C port 0, then the module will load the default configuration that is stored in BIOS.

Para obtener información más completa sobre las optimizaciones del compilador, consulte nuestro Aviso de optimización.