Intel has updated the design guide and datasheet for the Intel® Joule™ compute module.

For those designing a carrier board that interfaces with the Intel® Joule™ compute module, we want to make sure you’re aware that the compute module contains several signals that act as module “boot strap” signals, which are latched during the module boot process. These boot strap signals are listed in required strapping of module pins in the Intel® Joule™ module datasheet. In order to ensure that the module boots properly, the expansion board designer must isolate expansion board circuitry from the module’s boot strap signals during the boot process. Failure to provide proper isolation may result in the module failing to boot or module features disabled.

The Intel® Joule™ compute module provides a signal, PMIC_PWRGOOD, that can be used to determine when the boot process is complete and thus should be used to enable and disable the isolation circuitry. Expansion board designs should implement isolation circuitry as recommended in the block diagram below, and that meets the timing requirements of the table below and the timing diagram below.

Referring to the block diagram below, the isolation circuit block can also be used to level shift the module’s 1.8V IO signals to 3.3V or 5.0V logic levels, provided that the specifications of the table below are met.

Recommended Block Diagram for Boot Strap Signal Isolation

Example of a Delay Circuit you might use

PMIC_PWRGOOD to Isolation Circuitry Timing Diagram

PMIC_PWRGOOD and Boot Strap Signal Electrical Specifications

Parameter Description Min Typ Max Units
TDISABLE Time between PMIC_PWRGOOD assertion to ENABLE_N deassertion (e.g. disabling of isolation circuit) 200     us
TENABLE Time between PMIC_PWRGOOD deassertion to ENABLE_N assertion (e.g. enabling of the isolation circuit) 0   1 ms
RISOLATION_5V Minimum Isolation Impedance (A to B) for 5V level shifting 800     kohms
RISOLATION_3.3V Minimum Isolation Impedance (A to B) for 1.8V and 3.3V level shifting 500     kohms

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