Zona para desarrolladores Intel®:
Rendimiento

Destacado

¡Recién publicado! Intel® Xeon Phi™ Coprocessor High Performance Programming 
Aprenda los principios básicos de la programación para esta nueva arquitectura y nuevos productos. ¡Nuevo!
Intel® System Studio
Intel® System Studio es una solución en forma de suite completa de herramientas de desarrollo de software integrado que puede acelerar el tiempo de inserción en el mercado, fortalecer la fiabilidad del sistema e impulsar el consumo eficaz de energía y el rendimiento. ¡Nuevo!
Si no pudo asistir: Reproducción del webinario en vivo de 2 días
Introducción al Desarrollo de aplicaciones de alto rendimiento para coprocesadores Intel® Xeon e Intel® Xeon Phi™.
Structured Parallel Programming
Los autores Michael McCool, Arch D. Robison y James Reinders utilizan un método basado en patrones estructurados que debería poner el tema al alcance de todos los desarrolladores de software.

Brinde el mejor desempeño de su aplicación a sus clientes mediante la programación en paralelo con la ayuda de los recursos innovadores de Intel.

Recursos de desarrollo


Herramientas de desarrollo

 

Intel® Parallel Studio

Oferta de paralelismo simplificado, de principio a fin, a desarrolladores de Microsoft Visual Studio* C/C++, Intel® Parallel Studio proporciona herramientas avanzadas para optimizar las aplicaciones de clientes para procesadores multi-core y manycore.

Productos Intel® para desarrollo de software

Examine todas las herramientas que le ayudan a optimizar para la arquitectura Intel.Ciertas herramientas están disponibles para una evaluación gratuita por 45 días.

Base de conocimiento de herramientas

Encuentre guías e información de asistencia técnica sobre las herramientas de Intel.

List of Useful Power and Power Management Articles, Blogs and References
By Taylor Kidd (Intel)Posted 04/17/20142
INTRODUCTION AND PURPOSE: This article endeavors to provide a single point of reference to Power Management blogs, articles and other resources relevant to the Intel® Xeon Phi™ coprocessor. There are many excellent resources out there on power, power management and tools; this article cannot ho...
Power Management States: P-States, C-States, and Package C-States
By Taylor Kidd (Intel)Posted 04/17/20140
(For a PDF version of this article, download the attachment.) Contents Preface: What, Why and from Where. 1 Chapter 1: Introduction and inquiring minds. 2 Chapter 2: P-States, Reducing power consumption without impacting performance. 3 Chapter 3: Core C-States, The Details. 5 Chapter 4: ...
A Parallel Stable Sort Using C++11 for TBB, Cilk Plus, and OpenMP
By Arch D. Robison (Intel)Posted 04/11/20140
This article describes a parallel merge sort code, and why it is more scalable than parallel quicksort or parallel samplesort. The code relies on the C++11 “move” semantics. It also points out a scalability trap to watch out for with C++. The attached code has implementations in Intel® Threading ...
Intel® Software Development Tools 2015 Beta
By Gergana Slavova (Intel)Posted 03/27/20140
Contents What's New Details Frequently Asked Questions Beta duration Support How to enroll in the Beta program Beta Webinars Known Issues and Special Features Next Steps   What's New in the 2015 Beta This suite of products brings together exciting new technologies along...

Páginas

Suscribirse a
No se encontró contenido
Suscribirse a Blogs de la Zona para desarrolladores Intel®
Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1
By kathy-farrel (Intel)0
Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1 - What's New - Webinar Tuesday, September 17 9am PDT Please join us for a technical presentation on the new features found in the recently released Intel® Parallel Studio XE 2013 SP1 Intel® Cluster Studio XE SP1. This release includes support for compilers and performance analysis on Intel® Xeon Phi™ on Windows*. The technical presentation will briefly cover new features for both C++ and Fortran on Linux*, Windows*, and OS X* operating systems as well as error checking and performance profiling tools. Learn how to efficiently boost your application performance! Not too late! - Register Now  Learn about Upcoming Webinars
Locking CPU cache lines for a thread ( L1)
By Younis A.4
Hi I'm working on securing access to L1 cache by locking it line by line. Is there any way to do it? For example, two threads accessing the L1 and L1 lines are locked for a certain time to each thread accessed them. Regards, Younis
Responsive OpenMP Theads in Hybrid Parallel Environment
By Don K.1
I have a Fortran code that runs both MPI and OpenMP.  I have done some profiling of the code on an 8 core windows laptop varying the number of mpi  tasks vs. openmp threads and have some understanding of where some performance bottlenecks for each parallel method might surface.  The problem I am having is when I port over to a Linux cluster with several 8-core nodes.  Specifically, my openmp thread parallelism performance is very poor.  Running 8 mpi tasks per node is significantly faster than 8 openmp threads per node (1 mpi task), but even 2 omp threads + 4 mpi tasks runs was running very slowly, more so than I could solely attribute to a thread starvation issue.  I saw a few related posts in this area and am hoping for further insight and recommendations in to this issue.  What I have tried so far ... 1.  setenv OMP_WAIT_POLICY active      ## seems to make sense 2.  setenv KMP_BLOCKTIME 1          ## this is counter to what I have read but when I set this to a large number (2500...
Optimizing cilk with ternary conditional
By Fabio G.3
What is the best way to optimize the cycle cilk_for(i=0;i<n;i++){ x[i]=x[i]<0?0:x[i]; }or somethings like that? Thanks, Fabio
have asked them to
By Robert P.0
ICC t20 World Cup 2014 Live StreamIndia vs Pakistan Live Stream
Optimizing reduce_by_key implementation using TBB
By Shruti R.0
Hello Everyone, I'm quite new to TBB & have been trying to optimize reduce_by_key implementation using TBB constructs. However serial STL code is always outperforming the TBB code! It would be helpful if I'm given an idea about how reduce_by_key can be improvised using tbb::parallel_scan. Any help at the earliest would be much appreciated. Thanks.
reading a shared variable
By VIKRANT G.3
hello everyone I am relatively new to parallel programming and have the following doubt:- is reading a shared variable(that is not modified by any thread) without using locks a good practice thanks for the help in advance  
Weird Openmp bug
By Cheng C.1
Dear all, I want to combine OpenMP and RSA_public_encrypt and RSA_private_decrypt routines. However, I was confused by a weird bug for a few days.    In the attached program, if I generated 2 threads for parallel encryption and decryption, everything works well. If I generated 3 or more threads, the RSA_public_encrypt routine works fine. All strings are successfully encrypted (encrypt_len=256). However, the RSA_private_decrypt routine went wrong, that is, only one thread works properly, all the other threads failed to decrypt some of the strings (decrypt_len=-1, rsa_eay_private_decrypt padding check failed). If there are 1000 strings and 4 threads, the total number of string failed to decrypt went around 710 (some times as low as around 200). So as expected, if I use 4 threads for parallel RSA_public_encrypt and one thread for RSA_private_decrypt, nothing went wrong.   It would be great if you could give some ideas. Thanks very much.    #include <openssl/rsa.h> #include <...

Páginas

Suscribirse a Foros

Destacado

Haga que el rendimiento prospere - Usando la innovación de código abierto desarrollado por las herramientas Intel ›


¡Obtenga LA GUÍA y empiece de inmediato! Subprocesamiento de aplicaciones, administración de memorias, herramientas de programación y sincronización.
Guía Intel para desarrollar aplicaciones con multi-subprocesos ›


¡Rápido, fácil y gratis!
Intel® Concurrency Checker ›


Imagine el futuro ahora.
Intel® AVX ›


Intel® Parallel Studio XE
Reciba un software para evaluación gratis ›