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  1. Buscar | Software Intel®

    https://software.intel.com/es-es/search/gss/mtrr?page=2

    24 Ene 2009 ... ... msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm constant_tsc pni monitor ds_cpl .

  2. Cache-references and Cache-misses counters

    https://software.intel.com/es-es/forums/intel-performance-tuning-utility/topic/288159

    16 Ago 2010 ... Using the linux /proc/mtrr i have configured all physical memory space to be uncachable.I have then ran 'perf stat myapp' and looked on the ...

  3. Compiling gsl 1.15 with Intel 12.1

    https://software.intel.com/es-es/forums/intel-c-compiler/topic/279461

    Feb 29, 2012 ... ... pae mce cx8 apic mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs ...

  4. cl_khr_fp64 unsupported message on Xeon processor

    https://software.intel.com/es-es/node/632400

    May 16, 2016 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts mmx fxsr sse sse2 ss ht syscall nx rdtscp lm ...

  5. Make sure certain PCIe writes are 64bytes to improve the bus ...

    https://software.intel.com/es-es/node/685125

    Sep 13, 2016 ... Note that the memory type depends on both the MTRR and the PAT for the address in question. This is described in Chapter 11 of Volume 3 of ...

  6. Is it possible to access RAM directly while the memory is cached?

    https://software.intel.com/es-es/forums/software-tuning-performance-optimization-platform-monitoring/topic/419444

    20 Ago 2013 ... Can I achieve by changing the memory type of X into Uncachable (by setting MTRR)? If not, is it possible at all? Thanks! RSS Inicio.

  7. Cache Enabled/Disabled?

    https://software.intel.com/es-es/forums/software-tuning-performance-optimization-platform-monitoring/topic/278571

    27 Abr 2012 ... Myassumption is that ifthe MTRR and PAT are writeback and Iset the CD&NW bits of CR0 then all levels of cacheare disabled. But if I clear the ...

  8. Can we use SSE intrinsics to write to a memory mapped PCI device ...

    https://software.intel.com/es-es/forums/software-tuning-performance-optimization-platform-monitoring/topic/590336

    Aug 27, 2015 ... Table 11-7 of Vol 3 of the SW Developer's manual (document 325384) shows how the combination of MTRR's and PAT's controls the caching ...

  9. Compile Pardiso example under linux

    https://software.intel.com/es-es/forums/intel-math-kernel-library/topic/298638

    22 Ene 2009 ... wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm ...

  10. SGX and SGX1 of CPUID with SKL emulation

    https://software.intel.com/es-es/forums/intel-software-guard-extensions-intel-sgx/topic/609769

    10 Feb 2016 ... ... +AVX +F16C +RDRAND +FPU +VME +DE +PSE +TSC +MSR +PAE +MCE + CX8 +APIC +SEP +MTRR +PGE +MCA +CMOV +PAT +PSE36 ...

  11. Bug in GESDD (but not GESVD)

    https://software.intel.com/es-es/forums/intel-distribution-for-python/topic/628049

    Apr 25, 2016 ... fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb ...

  12. centos6.5 composer_xe_2013_sp1.2.144 libiomp5.so painc

    https://software.intel.com/es-es/forums/intel-open-source-openmp-runtime-library/topic/539027

    21 Ene 2015 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx ...

  13. Ambiguity with CR3-store/load exiting settings

    https://software.intel.com/es-es/forums/virtualization-software-development/topic/484882

    22 Oct 2013 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx ...

  14. Does new Vtune include “LOAD_DISPATCH.ANY” event?

    https://software.intel.com/es-es/node/699368

    10 Oct 2016 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx ...

  15. Gzip error when downloaded file is untar'ed

    https://software.intel.com/es-es/forums/intel-cilk-software-development-kit/topic/291388

    19 Feb 2010 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm pni ...

  16. dgelsd on AMD processor

    https://software.intel.com/es-es/forums/intel-math-kernel-library/topic/288892

    28 Jun 2010 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext lm 3dnowext ...

  17. xHOST equals what?

    https://software.intel.com/es-es/forums/intel-c-compiler/topic/298613

    24 Ene 2009 ... ... msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm syscall lm constant_tsc pni monitor ds_cpl ...

  18. Compiling linux kernel 2.6.5 with icc

    https://software.intel.com/es-es/forums/intel-c-compiler/topic/310348

    16 Abr 2004 ... Unfortunately the compilation process always stops with the following error message: arch/i386/kernel/cpu/mtrr/if.c(164): error: expression must ...

  19. Configuring RAPL limits in Sandy Bridge Xeon processors

    https://software.intel.com/es-es/forums/software-tuning-performance-optimization-platform-monitoring/topic/389596

    18 Abr 2013 ... flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx ...

  20. no-fill mode in sandy bridge

    https://software.intel.com/es-es/forums/software-tuning-performance-optimization-platform-monitoring/topic/392495

    May 12, 2013 ... And I am sure that I have the correct memory type(WB in the experiment, both is mtrr and pat) and the process is restricted in a single core with ...

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