To use HLE/RTM to improve lock scalability the lock library needs to be enabled.
After applying a new technology (a new processor, a hardware accelerator, a new instruction, etc) besides measuring the immediate performance delta one requires a method to verify that this technol
By now, many of you have heard of Intel® Transactional Synchronization Extensions (Intel® TSX).
Intel recently released the 4th Generation Intel® Core™ processors, which have Intel® Transaction
In a previous post I discussed the Intel® Tra
Lock elision is a new way to scale programs. It requires following some rules for correctness and good performance.