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Exploring Intel® Transactional Synchronization Extensions with Intel® Software Development Emulator

Intel® Transactional Synchronization Extensions (Intel® TSX) is perhaps one of the most non-trivial extensions of instruction set architecture introduced in the 4th generation Intel® Cor

Autor Roman Dementiev (Intel) Última actualización 06/07/2019 - 17:00
Article

Bitonic Sorting

Demonstrates how to implement an efficient sorting routine with the OpenCL™ technology that operates on arbitrary input array of integer values. The sample uses properties of bitonic sequence and principles of sorting networks and enables efficient SIMD-style parallelism through OpenCL vector data types. The code is designed to work well on modern CPUs.
Autor Última actualización 31/05/2019 - 14:40
Article

Simple Optimizations of OpenCL™ Code

Simple Optimizations sample demonstrates simple ways of measuring the performance of OpenCL™ kernels in an application. It describes basics of profiling and important caveats like having dedicated “warming” run. It also demonstrates several simple optimizations, some of optimizations are rather CPU-specific (like mapping buffers), while others are more general (like using relaxed-math). The...
Autor Última actualización 31/05/2019 - 14:10
Mensajes en el blog

Applying Intel® Threading Building Blocks Observers for Thread Affinity on Intel® Xeon Phi™ Coprocessors

In spite of the fact that the Intel® Threading Building Blocks (Intel® TBB) library [1] [2] provides high-level task based parallelism intended to hide sof

Autor Alex (Intel) Última actualización 01/08/2019 - 09:30
Article

Using Basic Capabilities of Multi-Device Systems with OpenCL™

Download for Windows*

Autor Última actualización 31/05/2019 - 14:10
Article

Code Sample: Exploring MPI for Python* on Intel® Xeon Phi™ Processor

Learn how to write an MPI program in Python*, and take advantage of Intel® multicore architectures using OpenMP threads and Intel® AVX512 instructions.
Autor Nguyen, Loc Q (Intel) Última actualización 06/07/2019 - 16:30
Article

Intel® Intelligent Storage Acceleration Library: Cryptographic Hashes for Cloud Storage

Storage efficiency technologies like compression and deduplication with rapid generation of cryptographic hashes are available now via the Intel® Intelligent Storage Acceleration Library (Intel® ISA-L). Code sample illustrates how to use this powerful feature.
Autor Thai Le (Intel) Última actualización 06/07/2019 - 16:40
Article

How to use the MPI-3 Shared Memory in Intel® Xeon Phi™ Processors

Code Sample included: Learn how to use MPI-3 shared memory feature using the corresponding APIs on the Intel® Xeon Phi™ processor.
Autor Nguyen, Loc Q (Intel) Última actualización 06/07/2019 - 16:30
Article

Performance of Classic Matrix Multiplication Algorithm on Intel® Xeon Phi™ Processor System

Matrix multiplication (MM) of two matrices is one of the most fundamental operations in linear algebra. The algorithm for MM is very simple, it could be easily implemented in any programming language. This paper shows that performance significantly improves when different optimization techniques are applied.
Autor Última actualización 14/06/2019 - 11:50