This is a "cheatsheet" comparing the Fortran and C++ offload directives and functions in the context of programming for the Intel® Xeon Phi™ coprocessor
Many Faces of Parallelism: Porting Programs to the Intel® Many Integrated Core Architecture
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This article describes how to implement and optimize a three-dimension isotropic kernel with finite differences to run on the Intel® Xeon® Processor and Intel® Xeon Phi™.
How to efficiently use Multi-Channel DRAM (MCDRAM) and synchronous dynamic random-access memory.
Learn techniques for vectorizing code, adding thread-level parallelism, and enabling memory optimization.
This is an exercise in performance optimization on heterogeneous Intel architecture systems based on multi-core processors and manycore (MIC) coprocessors.
Exercise in performance optimization on Intel Architecture, including Intel® Xeon Phi™ processors.
To efficiently utilize all available resources for the task concurrency application on heterogeneous platforms, designers need to understand the memory architecture, the thread utilization on each platform, the pipeline to offload the workload to different platforms. To relieve designers of the burden of implementing the necessary infrastructures, the Heterogeneous Streaming (hStreams) library...