The code samples for the webinar "Further Vectorization Features of the Intel® Compiler" given on 4/7/2015 are attached below.
Multi-level parallelism with OpenMP* deserves your consideration—even if you've rejected it in the past. OpenMP nesting is turned off by default by most implementations.
Learn how to optimize some difficult loops with Intel® compilers for Fortran*, C, and C++.
The SIMD and multi-core features of modern processors enable large improvements in application performance―but only if the application is effectively optimized for parallel execution.
In this webinar, James Reinders, will cover the essential knowledge needed for effectively utilizing the extraordinary parallelism in the new Intel® Xeon Phi™ processor (code named Knights Landing)
The Intel’s 2nd generation Xeon Phi™ processor family x200 product (code-name Knights Landing) brings in new memory technology, a high bandwidth on package memory called Multi-Channel DRAM (MCDRAM)
We will describe, with C and Fortran examples, new opportunities for performance-enhancing vectorization provided by the Intel® AVX-512 instruction set on the processor code named Knights Landing.
Get an overview of the benefits of using this compiler with the Intel® Xeon® and Intel Xeon Phi™ coprocessors.
Intel offers several options for getting help with this compiler. Learn about them in this presentation.