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Mensajes en el blog

Seeing One TeraFlop/sec, the software side, and feeling a bit emotional

I've known this day was coming - but when I saw Knights Corner clearly sustaining a TeraFlop (DGEMM, wide range of block sizes) per second - I was surprised by my emotional reaction inside.

Autor James R. (Blackbelt) Última actualización 21/03/2019 - 12:08
Article

Tuning Guides and Performance Analysis Papers

Microarchitecture-specific guides to tuning and optimizing application performance with Intel® VTune™ Amplifier.
Autor MrAnderson (Intel) Última actualización 10/05/2019 - 10:48
Article

Experimental Cloud-based Ray Tracing Using Intel® MIC Architecture for Highly Parallel Visual Processing

The cloud is game-changing factor in computing. Companies are offering a service in which the game itself runs on servers in the cloud. It processes user interactions from the game client, & the server sends back a compressed, rendered image to the user.
Autor Daniel Pohl (Intel) Última actualización 06/07/2019 - 16:25
Mensajes en el blog

Knights Corner Micro-Architecture Support

How does a high performance SMP on-a-chip sound to you?

Autor James R. (Blackbelt) Última actualización 06/07/2019 - 16:40
Mensajes en el blog

Knights Corner: Open source software stack

Knights Corner: Open source software stack

Autor James R. (Blackbelt) Última actualización 06/07/2019 - 16:40
Article
Article

Programming for Multicore and Many-core Products including Intel® Xeon® processors and Intel® Xeon Phi™ X100 Product Family coprocessors

The programming models in use today, used for multicore processors every day, are available for many-core coprocessors as well. Therefore, explaining how to program both Intel Xeon processors and Intel Xeon Phi coprocessor is best done by explaining the options for parallel programming. This paper provides the foundation for understanding how multicore processors and many-core coprocessors are...
Autor James R. (Blackbelt) Última actualización 14/06/2019 - 12:10
Article

Effective Use of the Intel® Compiler Offload Features for Intel® MIC Architecture

Compiler Methodology for Intel® Many Integrated Core (Intel® MIC) Architecture

Autor Última actualización 21/03/2019 - 12:00
Article

Building a Native Application for Intel® Xeon Phi™ Coprocessors

Introduction
Autor AmandaS (Intel) Última actualización 14/06/2019 - 11:50