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Article

IDF15 - Webcast: Code Modernization Best Practices

Intel® Xeon® and Intel® Xeon Phi™ processor based platforms provide multiple levels of parallel execution resources. The amount of compute power of these resources is growing with every product generation, yet most applications do not fully utilize the available computing resources. This session will provide details on the growth in hardware resources and characterize performance using different...
Autor Última actualización 06/07/2019 - 11:37
Article

Improve Vectorization Performance with Intel® AVX-512

See how the new Intel® Advanced Vector Extensions 512CD and the Intel AVX512F subsets (available in the Intel® Xeon Phi processor and in future Intel Xeon processors) lets the compiler automatically generate vector code with no changes to the code.
Autor Alberto V. (Intel) Última actualización 08/07/2019 - 19:26
Article

A Structured Performance Optimization Framework for Simultaneous Heterogeneous Computing

Heterogeneous computing platforms with multicore host system and many-core accelerator devices have taken a major step forward in the mainstream HPC computing market this year with the announcement

Autor Última actualización 30/09/2019 - 17:30
Article

OpenMP Loop Collapse Directive

Compiler Methodology for Intel® MIC Architecture

Autor admin Última actualización 30/09/2019 - 17:30
Article

Data Alignment to Assist Vectorization

Compiler Methodology for Intel® MIC Architecture

Autor Rakesh Krishnaiyer (Intel) Última actualización 30/09/2019 - 17:30
Article

Whatever the Weather: The Intel Five Step Framework for Code Modernization

Weather forecasting is a crucial aspect of modern life, enabling efficient planning and logistics, while also protecting life and property through timely warnings of severe conditions. But accurate, long-range weather prediction is extremely complex, often involving enormous data sets and requiring code that is optimized to leverage the most advanced computer hardware features available.
Autor Última actualización 30/09/2019 - 17:30
Article

Scheduling for 1-4 Threads Per Core Using Compiler Option -qopt-threads-per-core

Compiler Methodology for Intel® MIC Architecture

Autor admin Última actualización 30/09/2019 - 17:30
Article

Usando o Intel® Inspector nos nós acelerados do NCC/UNESP

Daniel Massaru Katsurayama, Jairo Panetta, Simone Shizue Tomita Lima

Autor Jairo P. Última actualización 30/09/2019 - 17:30
Article

Memory Allocation and First-Touch

Compiler Methodology for Intel® MIC Architecture

Autor AmandaS (Intel) Última actualización 30/09/2019 - 17:30
Article

Performance Improvement Opportunities with NUMA Hardware

Intel’s non-uniform memory access (NUMA) strategy is based on several new memory technologies that promise significant improvements in both capability and performance. This article provides information on Multi-Channel DRAM (MCDRAM) and High-Bandwidth Memory (HBM), Non-volatile dual inline-memory modules (NVDIMMs), and Intel® Omni-Path Fabric (Intel® OP Fabric).
Autor Última actualización 30/09/2019 - 17:30