Intel® Transactional Synchronization Extensions (Intel® TSX) is perhaps one of the most non-trivial extensions of instruction set architecture introduced in the 4th generation Intel® Cor
Intel® TSX exposes a speculative execution mode to the programmer to improve locking performance.. Tuning speculation requires heavily on a PMU profiler.
To use HLE/RTM to improve lock scalability the lock library needs to be enabled.
After applying a new technology (a new processor, a hardware accelerator, a new instruction, etc) besides measuring the immediate performance delta one requires a method to verify that this technol
By now, many of you have heard of Intel® Transactional Synchronization Extensions (Intel® TSX).
Intel recently released the 4th Generation Intel® Core™ processors, which have Intel® Transaction
Lock elision is a new way to scale programs. It requires following some rules for correctness and good performance.
Starting with version 7.12.0, Intel® SDE has Intel® TSX-related instruction and memory access logging features which can be useful for debugging Intel® TSX's capacity aborts.