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Intel® Software Development Emulator Download

Download page for the latest Intel® Software Development Emulator
Autor Ady Tal (Intel) Última actualización 03/07/2019 - 20:00
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Exploring Intel® Transactional Synchronization Extensions with Intel® Software Development Emulator

Intel® Transactional Synchronization Extensions (Intel® TSX) is perhaps one of the most non-trivial extensions of instruction set architecture introduced in the 4th generation Intel® Cor

Autor Roman Dementiev (Intel) Última actualización 06/07/2019 - 17:00
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Intel® Transactional Synchronization Extensions (Intel® TSX) profiling with Linux perf

Intel® TSX exposes a speculative execution mode to the programmer to improve locking performance.. Tuning speculation requires heavily on a PMU profiler.

Autor Andreas Kleen (Intel) Última actualización 04/07/2019 - 17:00
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Using HLE and RTM with older compilers with tsx-tools

To use HLE/RTM to improve lock scalability the lock library needs to be enabled.

Autor Andreas Kleen (Intel) Última actualización 14/06/2017 - 13:26
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Web Resources About Intel® Transactional Synchronization Extensions

A list useful technical resources related to Intel® Transactional Synchronization Extensions (Intel® TSX)
Autor Roman Dementiev (Intel) Última actualización 23/07/2019 - 09:12
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Monitoring Intel® Transactional Synchronization Extensions with Intel® PCM

After applying a new technology (a new processor, a hardware accelerator, a new instruction, etc) besides measuring the immediate performance delta one requires a method to verify that this technol

Autor Roman Dementiev (Intel) Última actualización 04/07/2019 - 17:00
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Fun with Intel® Transactional Synchronization Extensions

By now, many of you have heard of Intel® Transactional Synchronization Extensions (Intel® TSX).

Autor Última actualización 04/07/2019 - 17:00
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Transactional memory support: the speculative_spin_mutex

Intel recently released the 4th Generation Intel® Core™ processors, which have Intel® Transaction

Autor Última actualización 28/05/2018 - 18:30
Article

TSX anti patterns in lock elision code

Lock elision is a new way to scale programs. It requires following some rules for correctness and good performance.

Autor Andreas Kleen (Intel) Última actualización 07/06/2017 - 10:53
Article

Analyzing Intel® SDE's TSX-related log data for capacity aborts

Starting with version 7.12.0, Intel® SDE has Intel® TSX-related instruction and memory access logging features which can be useful for debugging Intel® TSX's capacity aborts.

Autor Última actualización 06/07/2019 - 10:52