By now, many of you have heard of Intel® Transactional Synchronization Extensions (Intel® TSX).
Intel® SDE includes a software validation mechanism to restrict executed instructions to a part
Intel recently released the 4th Generation Intel® Core™ processors, which have Intel® Transaction
In a previous post I discussed the Intel® Tra
Lock elision is a new way to scale programs. It requires following some rules for correctness and good performance.
Starting with version 7.12.0, Intel® SDE has Intel® TSX-related instruction and memory access logging features which can be useful for debugging Intel® TSX's capacity aborts.