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TSX fallback paths

The need for fallback paths
Autor Andreas Kleen (Intel) Última actualización 14/06/2017 - 13:26
Mensajes en el blog

Fun with Intel® Transactional Synchronization Extensions

By now, many of you have heard of Intel® Transactional Synchronization Extensions (Intel® TSX).

Autor Última actualización 04/07/2019 - 17:00
Article

Using Intel® SDE's chip-check feature

Intel® SDE includes a software validation mechanism to restrict executed instructions to a part

Autor Mark Charney (Intel) Última actualización 31/05/2019 - 09:04
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Transactional memory support: the speculative_spin_mutex

Intel recently released the 4th Generation Intel® Core™ processors, which have Intel® Transaction

Autor Última actualización 28/05/2018 - 18:30
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Transactional Memory Support: the speculative_spin_rw_mutex (Community Preview Feature)

In a previous post I discussed the Intel® Tra

Autor Última actualización 14/06/2017 - 15:46
Article

TSX anti patterns in lock elision code

Lock elision is a new way to scale programs. It requires following some rules for correctness and good performance.

Autor Andreas Kleen (Intel) Última actualización 07/06/2017 - 10:53
Mensajes en el blog

Intel® Xeon® E5-2600 v3 Product Family

Autor Nguyen, Khang T (Intel) Última actualización 06/07/2019 - 19:20
Article

Analyzing Intel® SDE's TSX-related log data for capacity aborts

Starting with version 7.12.0, Intel® SDE has Intel® TSX-related instruction and memory access logging features which can be useful for debugging Intel® TSX's capacity aborts.

Autor Última actualización 06/07/2019 - 10:52
Article

Intel® Xeon® Processor E7 v3 Product Family

Autor Nguyen, Khang T (Intel) Última actualización 06/07/2019 - 16:40