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Brinde un rendimiento superior a las aplicaciones y, al mismo tiempo, minimice el tiempo y esfuerzo para desarrollar, afinar y probar aplicaciones.

Una guía concisa para las herramientas de programación en paralelo para los procesadores Intel® Xeon®
Elija los modelos y herramientas correctos de programación para incrementar el desempeño de la aplicación.

Descargue SDK de Intel® OpenCL
El primer estándar abierto y sin regalías para la programación en paralelo para fines generales.

Parallel Studio XE 2013 está aquí
Herramientas poderosas para aprovechar al máximos los clústeres y supercomputadoras.

Opciones del Compilador Intel® para Intel® SSE e Intel® AVX
Familiarícese con los tres tipos principales de optimizaciones específicas para el procesador.

Intel le ofrece una gran variedad de capacidades a fin de optimizar sus aplicaciones para mejorar el rendimiento, consumo de energía, seguridad y disponibilidad. Haga clic en cada uno de los botones a continuación para ver qué recursos tiene a su disposición.

Intel ofrece una variedad de servidores, microservidores y coprocesadores para abordar una variedad de necesidades de nube, de computación técnica y de procsos empresariales. Los recursos siguientes permiten comparar las características desde una perspectiva de hardware.

En esta página encontrará información sobre los productos más recientes lanzados por Intel, la cual se presenta con una perspectiva más centrada en el software: la arquitectura y las características, los aspectos claves de habilitación del software y la forma en que se utilizan o configuran los productos a fin de ofrecer el mejor desempeño.

Otros recursos útiles:

Resolving Symbols for Intel® Manycore Platform System Stack (Intel® MPSS) in Intel® VTune™ Amplifier XE Analysis
By Sumedh Naik (Intel)Posted 04/09/20140
Background Whenever Intel VTune Amplifier XE is unable to resolve symbols for libraries or the operating system, it lumps all the counts for that module together. Often, these lumped counts end up at the top of the hotspot list, skewing the analysis. By setting the correct search library path in...
Recipe: Building and Optimizing the Hogbom Clean Benchmark for Intel® Xeon Phi™ Coprocessors
By Sumedh Naik (Intel)Posted 04/09/20140
Overview This article provides a recipe for compiling and running the Hogbom Clean benchmark for the Intel® Xeon Phi™ coprocessor and discusses the various optimizations applied to the code.  Introduction Hogbom Clean is a part of the ASKAP benchmark package. The ASKAP benchmark package is use...
Debugging Intel® Xeon Phi™ Applications on Linux* Host
By Georg Zitzlsberger (Intel)Posted 04/09/20140
Contents Introduction Debug Solution for Intel® MIC How to get it? Why use the provided GNU* GDB from Intel? Why is Intel providing a Command Line and Eclipse* IDE Integration? Deprecation Notice Features Register and Instruction Set Support Data Race Detection Debugging...
Debugging Intel® Xeon Phi™ Applications on Windows* Host
By Georg Zitzlsberger (Intel)Posted 04/09/20143
Contents Introduction Debug Solution for Intel® MIC How to get it? Debug Solution as Integration Components Required Configure & Test Prerequisite for Debugging Debugging Applications with Offload Extension Characteristics of Debugging Setting Breakpoints Start Deb...

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Instruction set extensions programming reference, revision 18
By Mark Charney (Intel)0
In early February, an updated instruction set extensions programming reference, revision 18, has been posted here.  It includes information about: Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions Intel® Secure Hash Algorithm (Intel® SHA) extensions  Intel® Memory Protection Extensions (Intel® MPX)  For more information about the technologies: http://www.intel.com/software/isa
Updated Intel® Software Development Emulator
By Ady Tal (Intel)0
Hello, we just released version 6.20 of the Intel® Software Development Emulator. It is available here:http://www.intel.com/software/sde It includes: Added support for XSAVEC and CLFLUSHOPT. Disabled TSX CPUID bits when TSX emulation is not requested. Improved disassembly for MPX instructions. Added an option for running chip-check only on the main executable. Added support for -quark (Pentium ISA). Added application debugging for Mac OSX with the lldb debugger.
Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1
By kathy-farrel (Intel)0
Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1 - What's New - Webinar Tuesday, September 17 9am PDT Please join us for a technical presentation on the new features found in the recently released Intel® Parallel Studio XE 2013 SP1 Intel® Cluster Studio XE SP1. This release includes support for compilers and performance analysis on Intel® Xeon Phi™ on Windows*. The technical presentation will briefly cover new features for both C++ and Fortran on Linux*, Windows*, and OS X* operating systems as well as error checking and performance profiling tools. Learn how to efficiently boost your application performance! Not too late! - Register Now  Learn about Upcoming Webinars
Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
By Roman Dementiev (Intel)4
Hi, you might find this collection of technical material about Intel TSX instructions useful: http://www.intel.com/software/tsx By a suggestion from some senior forum contributors I am making this post sticky. Best regards, Roman
Links to instruction documentation
By Thomas Willhalm (Intel)24
The Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A and 2B (available here) are the instruction set reference. Haswell (2013) new instructionsare in theprogrammer's reference manual. In appendix C of the Intel 64 and IA-32 Architectures Optimization Reference Manual (available here), the latencies and throughput of instructions are listed. The documentation of the Intel C++ Compiler contains documentation of the intrinsics. The AVX Programming Reference and examples for using AVX are available on the AVX community page. (The interactive Intel Intrinsics Guide is also available there, which is useful for SSE programming as well.) The Intel Software Development Emulator (Intel SDE) allows simulation of future instructions.
think-tank is working
By Robert P.0
IPL 2014 Live StreamReal Madrid vs Barcelona Live Stream
Problem when using RTM
By geomap0
Hello, My name is George Mappouras and I am trying to make a simple program in order to evaluate the TSX in the new Haswell processors. However I came across a very strange problem that I can't find its cause and I was wondering if you could help me with it. The idea is simple, I have 'x' accounts and 'n' threads. Each thread does 'k' amount of transactions between random accounts (I transfer a random amount from account1 to account2 ). I tried this program with RTM, spinlocks and mutex (fine grained locking). In the end I check my results by comparing them to a single threaded version of this program. The problem is that in the case of the RTM (with or without fallback path) I noticed that sometimes the results don't match the single-threaded results.  I also noticed that this seems to happen only when I use hyperthreading. (The computer in which I test my program has 4 physical cores with hyperthreading, that means 8 threads max). I tried to debug my program and I suspect that the...
asm blocks
By berthou4
Hello, I am writing AVX code inside asm blocks (don"t want to use avx intrinsics). A lot of gp registers are used and so they are mixed with the ones generated by the compiler and thus it is screwing the behavior of the code pretty fast. Is there an automatic or manual way to avoid these register overlaps ? Any link to documentation would be great. I would like also to use asm blocks in fortan with ifort, but didn't find the way yet. Thanks Vincent

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