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Una guía concisa para las herramientas de programación en paralelo para los procesadores Intel® Xeon®
Elija los modelos y herramientas correctos de programación para incrementar el desempeño de la aplicación.

Descargue SDK de Intel® OpenCL
El primer estándar abierto y sin regalías para la programación en paralelo para fines generales.

Parallel Studio XE 2013 está aquí
Herramientas poderosas para aprovechar al máximos los clústeres y supercomputadoras.

Opciones del Compilador Intel® para Intel® SSE e Intel® AVX
Familiarícese con los tres tipos principales de optimizaciones específicas para el procesador.

Intel le ofrece una gran variedad de capacidades a fin de optimizar sus aplicaciones para mejorar el rendimiento, consumo de energía, seguridad y disponibilidad. Haga clic en cada uno de los botones a continuación para ver qué recursos tiene a su disposición.

Intel ofrece una variedad de servidores, microservidores y coprocesadores para abordar una variedad de necesidades de nube, de computación técnica y de procsos empresariales. Los recursos siguientes permiten comparar las características desde una perspectiva de hardware.

En esta página encontrará información sobre los productos más recientes lanzados por Intel, la cual se presenta con una perspectiva más centrada en el software: la arquitectura y las características, los aspectos claves de habilitación del software y la forma en que se utilizan o configuran los productos a fin de ofrecer el mejor desempeño.

Otros recursos útiles:

Tuning Guides and Performance Analysis Papers
By MrAnderson (Intel)Posted 08/16/20110
Intel® VTune™ Amplifier XE Tuning Guides Our tuning guides explain how to identify common software performance issues using VTune Amplifier XE, and give suggestions for optimization. Tuning Guide for Intel® Microarchitecture Processors Covered  code name Ivy Bridge-E* (se...
Performance comparison of the Cluster File Systems at the Intel CRT-DC
By adminPosted 06/22/20111
Executive summary The Intel Customer Response Team Data Center (called CRT-DC) located in DuPont/Washington is running benchmarking data center with >450 compute nodes. The cluster is known as Endeavour, rebuild on a regular basis with latest hardware and has been listed in Top 500 since 2006 ...
New Books
By adminPosted 05/02/20110
Intel® Xeon Phi™ Coprocessor High Performance ProgrammingJames Jeffers, James Reinders Learn the essentials of programming for this new architecture and new products. Structured Parallel ProgrammingMichael McCool, Arch D. Robison, and James Reinders An approach based on structured patterns whi...
DB2* 9 pureXML* Scalability on Intel® Xeon® MP Platforms Using IBM N Series* Storage
By adminPosted 03/24/20110
Introduction With the recent launch of the next-generation Intel® Xeon® processor MP, IBM DB2* 9, and IBM N Series storage, businesses can now enjoy the rich processing power and performance benefits these products have to offer. This paper unveils the combined performance of Dual-Core Intel® Xeo...

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Are my Parallel Studio packages updating or not?
By dnesteruk2
I've fired up the Intel Software Manager, pressed the download buttons and it all looks like this: So instead of pause buttons I get resume buttons. I've tried pressing them, they briefly turn into pause buttons. So my question: is anything being downloaded or is this thing broken? Thanks. P.S.: registration on this forum is atrocious. Finding this forum was next to impossible. The media upload thing is so far below I didn't notice it and uploaded elsewhere. Usability hint-hint!
mem address directly from SSE/AVX register
By Luchezar B.3
Hello, I would like to make a suggestion Very often [otherwise well vectorizible] algorithms require reading/writing from/to mem addresses which are calculated per-channel (reading from table, sampling a texture, etc.).When you get to this, you are forced to make that part of the algorithm scalar by extracting each channel in turn to a GP register, performing the memory operation and then inserting the result back to a vector register.I don't think a single instruction that interprets each channel as an address and reads/writes to different memory locations at once is hardware feasible (though it would be extremely good) but at least we could have something that would ease the situation. my suggestion is instructions for memory access that get the address directly from the sse/avx register: loadd $(i + (j<<4)), %xmm0, %xmm1 - read 32-bit word from address specified in the i-th dword of xmm0 and store it in j-th quarter of xmm1stored $(i + (j<<4)), %xmm0, %xmm1 - read 32-...
Studying Intel TSX Performance: strange results
By Alexander K.9
Dear all, I've made studying of Intel TSX performance - its abort cases and comparison with spin lock. The study with reference to source code is available at http://natsys-lab.blogspot.ru/2013/11/studying-intel-tsx-performance.html . I see some performance gain for TSX in comparison with spin lock. However I stll have few of questions: 1. I see huge jump of transactional aborts when transaction work set reaches 256 cache lines (Figure 1). This is 16KB which is just only a quarter of L1d cache. The workload is single threaded, running strictly on one CPU core. Also I didn't use HyperThreading. I know that the cache has 8-way associativity, however I used static memory allocations (which are continous in virtual memory and likely continous physically) and it's unlikely that I have too many collisions in cache lines to get only 16KB of available cache memory for the transaction. So how the spike can be explained? Also Figure 3 (dependency of execution time on transaction size) shows s...
Capacity planning
By aminer103
Hello, I have come to an interresting subject, if we have a distributed database and a webserver and HTML files and you want to do a capacity planning of your webserver this will complicate the things, cause the database server must be modelized as an hyperexponential distribution that is an M/G/1 queuing system , but as you have noticed since the database server system , in our network , comes before the internet connection that will be modeled as an M/M/1 queuing system, so you have to use a queuing network simulation to solve this problem , but if you have noticed, in capacity planning we have also to calculate the response time of the worst case performance, so this will easy the job for us cause in the worst case scenario since the M/G/1 queuing system of the database server have three exponential distributions for the reads and writes and deletes transactions, so we have to choose the worst service time that is exponentially distributed , so i think we have to choose only the...
Debug mic in Windows7
By Victor Z.1
 When I typed   "micnativeloadex MyTest -d 0" in Windows 7 to debug  MyTest.exe ( mic + OpenMP), I got the error  message below: Unable to create remote process. ssh to the coprocessor and run ps to verify the coi_daemon is executing. It may be necessary to restart the mpss service.      But there is no problem to run mic+openmp application.  I follow Intel debugger extersion for Intel MIC -VC2012. But it did work. How to debug it? Thank you in advance.
Parallel archiver and scalability
By aminer101
Hello, I think i am happy now, please read again... I have benchmarked parallel archiver using parallel LZMA using  5 threads on a quad core, so this have giving false results on the timing... So i have started parallel archiver with a single thread and this has giving a more accurate results, here is my correction please read again... I have come to an interresting subject, so be smart and follow with me please... I have tried to do a worst scalability prediction with an HDD hardiskfor my parallel archiver(you will find my parallel archiver here:http://pages.videotron.com/aminer/)  with Parallel LZMA, and i think it's worst than what i have thought.. there is four things in my Parallel LZMA algorithm: First we have to copy serially a stream from the hardisk to the memory and this will take in average 0.2  second and in the compression method we have to copy a stream to the memory and this will take in average 0.05 second and in the compression method you have to compress a stream ...
I have come to an interresting subject
By aminer100
Hello, I have come to an interresting subject, so be smart and follow with me please... I have tried to do a worst scalability prediction with an HDD hardiskfor my parallel archiver(you will find my parallel archiver here:http://pages.videotron.com/aminer/)  with Parallel LZMA, and i think it's worst than what i have thought.. there is four things in my Parallel LZMA algorithm: First we have to copy serially a stream from the hardisk to the memory and this will take in average 0.9 second and in the compression method we have to copy a stream to the memory and this will take in average 0.01 second and in the compression method you have to compress a stream to another stream in memory and this will take in average 3.1 seconds and in the compression method you have to copy a compressed stream to a hardisk file and this will take in average 0.01 second.     So we have the serial part that is: 0.9 second + 0.01 second  + 0.01 second and the parallel part will that is: 3.1 second So th...
Many-cores hit the memory wall
By aminer102
Many-cores hit the memory wall http://storagemojo.com/2008/12/08/many-cores-hit-the-memory-wall/ Thank you, Amine Moulay Ramdane.

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