Transactional memory

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  • Transactional Memory Support: the speculative_spin_rw_mutex (Community Preview Feature)

    In a previous post I discussed the Intel® Transactional Synchronization Extensions (Intel® TSX) technology released in the new generation of processors.  I described the Intel® Threading Building Blocks (Intel® TBB) implementation of the HLE interface (speculative_spin_mutex).  Now we can talk about the implementation of speculative_spin_rtw_mutex, a Preview Feature of TBB 4.2 Update 2.

    Transactional memory support: the speculative_spin_mutex

    Intel recently released the 4th Generation Intel® Core™ processors, which have Intel® Transactional Synchronization Extensions (Intel® TSX) enabled.  Intel TSX can improve the performance of applications that use lock-based synchronization to protect data structure updates.  This feature allows multiple non-conflicting lock-protected changes to data to occur in parallel.

    Fun with Intel® Transactional Synchronization Extensions

    By now, many of you have heard of Intel® Transactional Synchronization Extensions (Intel® TSX). If you have not, I encourage you to check out this page ( before you read further. In a nutshell, Intel TSX provides transactional memory support in hardware, making the lives of developers who need to write synchronization codes for concurrent and parallel applications easier.

    Coarse-grained locks and Transactional Synchronization explained

    Coarse-grained locks, and the importance of transactions, are key concepts that motivate why Intel Transactional Synchronization Extensions (TSX) is useful.  I’ll do my best to explain them in this blog.

    In my blog "Transactional Synchronization in Haswell," I describe new instructions (Intel TSX) that will improve the performance of coarse-grained locks.  Understanding coarse-grained locks and the concept of transactions are both key to understanding why Intel TSX matters.

    Software support for Transactional Memory

    Last week I attended Intel's annual Software Enabling Summit in Anaheim. This is a worldwide gathering of Intel's software engineers charged with ensuring that the world's software takes best advantage of Intel processor and platform features.

    (Sidebar: My wife thought it was really funny that we had a whole conference about "enabling", and suggested that I was now working with families and friends of those with addictions. No, not that kind of enabling, Deb.)

    Suscribirse a Transactional memory