While talking to a very intelligent but non-engineer colleague, I found myself needing to explain the threading and other components of the current and next generation Intel® Xeon Phi™ architectures. The first topic that came up was hyper-threading, and more specifically, the coprocessor’s version of hyper-threading. Wracking my brain, I finally hit upon an analogy that seemed to suit: the common kitchen.
The first step towards the usability of MCDRAM or High Bandwidth Memory (HBM) is assessing the memory bandwidth utilization for your application.
This article provides basic instructions on how to profile and evaluate memory bandwidth utilization for your application using Intel® Vtune™ Amplifier on Intel® Xeon® processors (IvyBridge/Haswell) and Intel® Xeon Phi™ Coprocessors (Knights Corner).
By Taylor Kidd, Intel Corporation
This article is essentially a collection of blogs I wrote on the same subject. The differences are simply a degree of formalism.
TABLE OF CONTENT:
The PDF document attached to this article contains a growing list of available, downloadable or work-in-progress code that can be run, or actively being optimized to run on Intel® Xeon Phi™ Coprocessors.
(Вы можете скачать PDF-версию этой статьи во вложении.)
This document gives platform designers, thermal engineers, hardware engineers, and computer architects instructions on how to acquire idle power readings from the Intel® Xeon Phi™ coprocessor.
I don’t know if any of you have noticed but Intel® has a tendency to emphasize its own homegrown tools. This isn’t bad as Intel has some of the best. Still, if someone has a favorite hammer, there’s a tendency to use that hammer for just about everything.
How about the future? Have we reached the pinnacle of power management?