Intel® Streaming SIMD Extensions

Instruction set extensions programming reference, revision 18

In early February, an updated instruction set extensions programming reference, revision 18, has been posted here. 

It includes information about:

  • Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions
  • Intel® Secure Hash Algorithm (Intel® SHA) extensions 
  • Intel® Memory Protection Extensions (Intel® MPX) 

For more information about the technologies:

Updated Intel® Software Development Emulator

Hello, we just released version 6.20 of the Intel® Software Development Emulator. It is available here:

It includes:

  • Added support for XSAVEC and CLFLUSHOPT.
  • Disabled TSX CPUID bits when TSX emulation is not requested.
  • Improved disassembly for MPX instructions.
  • Added an option for running chip-check only on the main executable.
  • Added support for -quark (Pentium ISA).
  • Added application debugging for Mac OSX with the lldb debugger.

Оптимизировали, оптимизировали, да не выоптимизировали!

Оптимизация? Конечно, каждый сталкивался с данной задачей при разработке своих, сколь-нибудь значительных, требующих определённых вычислений, приложений. При этом способов оптимизировать код существует огромное множество, и, как следствие, различных путей сделать это в автоматическом режиме с помощью опций компилятора. Вот здесь и возникает проблема – как выбрать то, что нужно нам и не запутаться?

asm blocks


I am writing AVX code inside asm blocks (don"t want to use avx intrinsics).

A lot of gp registers are used and so they are mixed with the ones generated by the compiler and thus it is screwing the behavior of the code pretty fast.

Is there an automatic or manual way to avoid these register overlaps ?

Any link to documentation would be great.

I would like also to use asm blocks in fortan with ifort, but didn't find the way yet.



SDE produces unstable behavior


I have some SSE/AVX code that I'm trying to test with Intel Software Development Emulator (SDE) on CPUs without the native support for some of the instruction set extensions. In particular, I tried the following setups:

1. Sandy Bridge CPU, SDE is running with -hsw switch.

2. Sandy Bridge CPU, SDE is running with -hsw -sse-sde switches.

3. A KVM guest virtual machine with SSE4 instructions (host CPU is Nehalem), SDE is running with -hsw switch.

All this is on Linux x86_64, SDE 6.22 and 6.12.

Disabling AVX

Hi all,

Is there a way (under Windows 7) to disable the support of AVX.
I wan't to make sure that on a pre-SB machine I don't get "Illegal Instruction exception".
Currently I have to use another machine and it's a bit annoying.

I don't use the /QaXXX flags because the code is already taking very long to compile (so it's taken care of manually) and I want it to work on Microsoft compiler too (even if performances would be degraded of course ;) ).

BKMs on the use of the SIMD directive

We had an ask from one of the various “Birds of a Feather” meetings Intel® holds at venues such as at the Super Computing* (SC) and International Super Computing* (ISC) conferences. The customer wanted to know BKMs (Best Known Methods) on the proper usage of the new OpenMP* 4.0 / Intel® Cilk™ Plus SIMD directive. I volunteered to create such a list. Investigating the topic more thoroughly, I discovered that there is already a vast amount of resources on vectorization and the use of the SIMD directive.

ippGetCpuFeatures for AVX2 support

I'm relying at the moment on inline ASM to check for AVX2 support, but use the IPP function ippGetCpuFeatures to check for AVX and SSEx features.

Using the IPP function is arguably a better solution (simple & clean) than inline ASM, so I have a comment in my code for the AVX2 checks along the line of "use the IPP stuff instead when available"

I'm doing some cleanup these days and I remarked a series of new flags in ippcore.h, but it looks like several of these new flags aren't explained in the latest IPP documentation.

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