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Security Advisory: Intel(R) MPSS affected by Shellshock bug

 

Recently there was a critical vulnerability exposed in the GNU* Bourne-Again Shell (Bash), the common command-line shell used in many Linux*/UNIX operating system.   This vulnerability also affects the operating system used for the Intel(R) Xeon Phi(tm) Coprocessor.  

Intel® Xeon Phi™ Coprocessor - ROADMAPS and Cluster BKMs

Attached to this thread is a PDF containing :

 - Guidance/communication on recent changes (and things Intel is considering) to make Cluster administration more straightforward

-  Calls out some tips and tricks which may be useful (especially with the latest MPSS release) 

- MPSS roadmaps (not cluster specific, general for all):   release cadence, OS support, OFED roadmaps, and features planned for MPSS 3.3

 

If you have feedback or concerns (on OS support, etc.), please let us know!

Intel(R) Xeon Phi(tm) Coprocessor -- Cluster training - call for demand!

Intel is evaluating to offer a 4 hour web-based basic tutorial covering the fundamental principles of how to integrate an Intel Xeon Phi coprocessor into a Linux based cluster.

During the course each attendant would have remote access to a Linux server and be able to do each step as shown in the outline below.  The course will be given free of charge. Requirements are an Internet connection, a web browser, and Putty.   We are settling on the sharing technology we will be using, and will publish that at a later date.

Troubleshooting HOWTO: Bad hardware? MPSS? Configuration?

Are you having problems with your hardware (Cannot see your Intel(R) Xeon Phi(tm) coprocessor?  Sporadic accessibility?) or with the Intel(R) Manycore Platform Software Stack (Intel(R) MPSS) running reliably?

Attached to this post are PDF "flowcharts" that explain how you can troubleshoot the problem (note:  Both Linux and Windows flowcharts are available), and shows what information you will want to collect if you need to escalate your issue to your OEM provider or Intel.

What collateral/documentation do you want to see?

Do you have questions that you are not finding the answers for in our documentation?  Need more training, source code examples, on what specifically?   Help us understand what's missing so that we can make sure we develop documentation you care about (what is important, and what is nice to have)!   Thank you

FAQS: Compilers, Libraries, Performance, Profiling and Optimization.

In the period prior to the launch of Intel® Xeon Phi™ coprocessor, Intel collected questions from developers who had been involved in pilot testing. This document contains some of the most common questions asked. Additional information and Best-Known-Methods for the Intel Xeon Phi coprocessor can be found here.

The Intel® Compiler reference guides can be found at:

Running OpenCV Computer Vision Programs on Xeon Phi

 

Hello,
I would like to know how to run opencv programs by using the intel xeon phi coprocessor card? What are my options? Also, how can i work with the Transparent API released by OpenCV and Xeon Phi ? Has Intel developed any module or support for running computer visions programs on the xeon phi?  Any suggestions or thoughts in this regard will be greatly appreciated.
Thankyou.

Trying to create an external bridge

Hi guys,

I'm trying to create an external bridge following the users guide from Intel.

First of all I execute the following command:

micctrl --addbridge=br0 --type=external --ip=<ip_HOST>

 

Then, I can see that a file ifcfg-br0 has created and I can see the bridge created with brctl show. Also I attached the eth1 interface to the bridge br0

 

Then, when I try execute:

 

micctrl --network=static --bridge=br0 --ip=<ip_MIC0>

 

I always obtain this error:

 

[Error] Bridge 'br0' not defined

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