Intel® Moderncode for Parallel Architectures

Application Threading Quickstart

Intel is offering a series ofonline developer workshops in June and July. You can register for these workshops here: The "Application Threading Quickstart" workshop is on June 14. Here's the abstract:

Get up to speed quickly on the methods and tools used to add threading to applications. See how to use tools to identify common issues which can cause incorrect behavior or poor performance in a threaded application.

leaveCriticalSection hang on Hyperthreaded P4?

We are experiencing a problem on a P4 3.06 with WinXP Pro SP2 that only occurs if hyperthreading is enabled. Our heavily multi-threaded application can hang for minutes, even hours. Debugging the hang reveals that two threads are stalled when releasing a critical section using leaveCriticalSection. The section itself is not owned by any thread, but the threads are not executing.

Should threads be part of C++ language?

Just read an article about a proposal that is shaping up to define new classes that would support threading as part of the C++ language ( Robert Buhr (U. of Waterloo) has developed micro-C++ to foster the developement of a larger set of threaded applications to take advantage of the upcoming multi-core processors.

Should these classes be adopted as part of the C++ language specification? I can think of three levels of threading:

AppCore bug found and fixed...

I found and fixed the last bug in AppCore wrt SMR and the node cache.
AppCore should now be basically bug free, I am currently verifying that. You
should probably re-download. Again, the bug is very subtle hard to trip. It
had to do with the way the lock-free single-producer/consumer queue
allocated its very first dummy node. The broken code simple did not set the
fp_dtor member of the dummy node to null. Stupid me!!!

Here is how you would reproduce it:
1. create a new queue object
2. enqueue/dequeue an object with Thread A

A couple of memory model questions

Can loads pass subsequent stores? Can a load from a storage location different than that of a subsequent load occur after the store? For example if the load location isn't in cache and the store location is in cache.

If yes, then I guess you need an MFENCE as a memory barrier to a store.release operation unless your prior accesses were just stores.

Dual-Core FAQ for Developers

All, I'm an ex-IDS editor writing up a draft of an FAQ for developers about dual-core. (It's going to be posted on IDS.) So I thought I'd check in this newsgroup to see if there any burning questions about dual-core chips that you'd like to see answered by Intel experts? Anything is fair game... including desktop (here today) and laptop and server (both coming relatively soon). Thanks for sharing your thoughts!
Geoff (gkoch AT stanfordalumni DOT org)

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