Intel ISA Extensions

Performance penalty for mixed AVX512 code?

There is a known performance penalty for mixing AVX with legacy code on today's Haswell processors.

  • Will this same problem exist in the Skylake chips and AVX512?
  • Will the delay be even longer for the ZMMs, since there are twice as many to save & restore and they are twice as long?
  • The workaround instruction for this, VZEROUPPER, is not listed as changed in Intel's Instruction Extensions manual. Won't there be changes like zeroing the high portion of the ZMM register?

This is documented by Intel:

Scaling TSX to multi-socket systems

Hi,

This is my first time posting here, sorry if this is in the wrong subforum.

To the best of my knowledge, TSX uses the L1 cache coherency protocol to monitor the read/write sets for a transaction. Something which I've been wondering for a while now is how would this scale to systems with >1 processors. I'm not familiar with how such systems maintain cache coherency at L1, but is it feasible for TSX to work correctly and efficiently in these kinds of systems?

Also, is this why the server variants of Haswell are only available for single socket systems?

SSE4 Intrensics on Visual Studio 2008

Hi,

Am optimizing my code application using Intel SSE intrinsic. It works fine with Intel compiler for 64-bit and 32-bit in MSVC 2008 IDE.

The same applications behaving differently with MSVC compiler for 32/64- bit run. I would like to know is there any limitation for MSVC 2008 IDE with respect to Intel SSE intrinsics( Am using upto SSE4.2).

Latest GCC to use with the SDE for MPX?

I'm aware there are links to download binary versions of GCC at https://software.intel.com/en-us/articles/intel-software-development-emu... however the latest experimental version of GCC appears to be quite more recent than this. However I'm confused about what branch I should be using if I want to build and use the latest MPX enabled development version of GCC with the Intel SDE.

Documentation bug for DIV/IDIV

I refer to the current Intel 64 and IA-32 Architectures Software Developer’s Manual (e.g. 325462-051US of June 2014).

For IDIV your will find that the upper bounds of quotient range is wrong for 32 and 64 bit; these must be e.g. -2^31..2^32-1 instead of -2^31..2^31-1.
Also, a description for signs the of the remainders are missing; AMD is more precise: "The sign of the remainder is always the same as the sign of the dividend, and the absolute value of the remainder is less than the absolute value of the divisor."

Working assembly example for MPX?

Does there already exist some small working example of an assembly program that enables MPX and demonstrates (some) of the instructions -- when executed in the SDE? I am aware that MPX appears to be enabled in libmpx. However I'd like to see this done by hand without using libmpx, assemble the program using an MPX enabled NASM and of course still run it in the SDE, just to play around with it.

I've already looked for this without finding anything, if someone could point me to such an already existing example that would be great.

When is AVX 512 on a chip, not just an emulator?

I'm having a really hard time finding anything other than rumors about this. I have seen the official statement that Broadwell chips will be available before Christmas, but I can't tell if Broadwell includes the AVX 512 extensions or not (I've heard both ways).  Anyone know for sure? Better yet can anyone point me to a link on intel.com that provides a definitive answer?

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