Virtualization Software Development

LBR and Virtualization

I'm using LBR to trace guest execution, each time before vm_enter I overwrite the MSR_LASTBRANCH_(N-1)_FROM_IP/TO values with a magic value (0xdeadbabe) and execute a few instructions and read out the values. sometimes a record is skipped in the LBR and contains the magic value.
why would this ever happen? I've look at the errata for haswell and didn't see anything similar, and running a similar code on the host outputs a perfect sequential trace. could this be an hardware bug related to vmx?

IOAT DMA / Crystal Beach 3 Specifications

Hi everyone,

I am looking for specifications for the Crystal Beach DMA controller. So far I only found the register specifications in the Xeon Processor Data sheet.

I've got a Ivy Bridge machine: Intel(R) Xeon(R) CPU E5-2670 v2 @ 2.50GHz running on an Intel Corporation C600/X79 series chipset.

We want to build a DMA driver for our research operating system (non Linux/Windows/solaris/bsd based). So I am basically looking for a specification to the following device i.e. how to setup the descriptor chains etc.

Virtualization Environment Utilized the Intel(R) Enterprise Class SSD

I recently published a blog on the benefits of Intel(R) Enterprise Class SSD that has the usage examples of the Intel(R) Enterprise Class SSD in the actual customer's environment. I figure that it might be useful for the developers in this forum to learn how other developers are using Intel hardware. 


The action of Accessed and Dirty bit for EPT

Hi there,

I write a piece of code to test the action of Accessed and Dirty bit of EPT in Intel(R) Core(TM) i3-4130 CPU @ 3.40GHz. Firstly I build a totally new EPT paging structure with A/D logging on, then run some operating system codes and log all the EPT violation (say trap log). At some point I paused the OS, parse the EPT paging structure and log all the entries built in the past period (say A/D log).

Here I get some interesting points:

[x86] Information request about the Global Descriptor Table (GDT) | Intel® Developer Zone


I am currently working on a forensics project (32 bits OS), and to reach one of my goals, I need to play a bit with the GDT. From what I understood, an instruction like call dword ptr [gs:0x10] does the following things :

handl I/O instruction caused VM-Exit

Hi, I'm writting code to handl I/O instruction caused VM-Exit, exit reason is 30.My guest is Windows XP.
After get information from Exit Qualification, I can handle insturctions when String instruction bit and REP prefixed bit is cleared.
But If these two bits are set, the trouble appears.
When I tried to read data from memory where guest ESI(or EDI) pointed, I want to translate the logical address into physical address contained in guest  ESI(or EDI). but during the tranlsation,  the Page Table is not presented.

Issue when the kernel parameter intel_iommu=on is being used


I am using DPDK 1.5 for development of host pmd for device “Connect X3”.

I am observing issue  while the ConnectX3 device DMA to a memory which is allocated with rte_memzone_reserve_aligned() API .

The issue(please refer ERROR below) has been observed if the system runs with the kernel parameter “intel_iommu=on”.

########## ERROR :##################################3

dmar: DRHD: handling fault status reg 302

dmar: DMAR:[DMA Write] Request device [01:00.0] fault addr 4f883000

DMAR:[fault reason 01] Present bit in root entry is clear

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