cache miss ratio for intel core i3

cache miss ratio for intel core i3

I have intel core i3 processor. I want to know the formulae for calculating cache miss rate for different level of caches i.e L1 L2 and L3. I have referred to the previous threads but since there are variants of formulae for the same i'm a little confused.

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If your i3 is Nehalem processor, please refer to this article to know formulas that you want.

Hi Peter
Thanks for your reply.
Yes my i3 330M is Nehalem Processor.But the link that you gave mentions that we can estimate the % of cycles due to long latency data access.
However i would like to know formulae for calculating L1/L2/L3 cache misses.
Are the formulae mentioned below correct?
1. L1: L1D_CACHE_LD.I_STATE / L1D_CACHE_LD. MESI
2. L2: (MEM_LOAD_RETIRED.LLC_UNSHARED_HIT + MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM) / L2_RQSTS.LOADS
3. L3: MEM_LOAD_RETIRED.LLC_MISS / (MEM_LOAD_RETIRED.LLC_UNSHARED_HIT + MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM)

Quoting tanvis1. L1: L1D_CACHE_LD.I_STATE / L1D_CACHE_LD. MESI
2. L2: (MEM_LOAD_RETIRED.LLC_UNSHARED_HIT + MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM) / L2_RQSTS.LOADS
3. L3: MEM_LOAD_RETIRED.LLC_MISS / (MEM_LOAD_RETIRED.LLC_UNSHARED_HIT + MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM)

The optimization guideline I mentioned last time, is to estimate the performanceimpact on program. I guess that you need the formulas to know "miss rates".

Above formulas are good in my view, you can use anythreshold - for example, .2 tojudge the result is good or bad.

Regard, Peter

Referring to the threadhttp://software.intel.com/en-us/forums/showthread.php?t=71832i found

L1 data cache miss rate= MEM_LOAD_RETIRED.L1D_MISS/

INST_RETIRED.ANY

For L2 data cache miss = MEM_LOAD_RETIRED.L2_MISS event/

INST_RETIRED.ANY

Are these for core 2 duo processors?

Please also mention what is the difference between MEM_LOAD_RETIRED.L1D_MISS event, and L1D_CACHE_LD.I_STATE event.

L1D_CACHE_LD counts L1D read and store, but MEM_LOAD_RETIRED.L1D counts L1D read only.

The ratio is defined by user,Misses can be divided by L1/L2/L3 access, INST_RETIRED, (with penalty) CPU_CLK_UNHALED, MEM_INST_RETIRED.LOADS, etc.

It depends onyour needs.

Regards, peter

Thanks for reply again.
Further i would like to know if i can measure L1/L2/L3 cache bandwidth using vtune?

You are welcome:-)

There is no predefined L1/L2/L3 bandwidth analysis in VTune.

Thereispredefined "memory bandwidth" analysis in VTune.

Regards, Peter

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