L3 cache events for new processors

L3 cache events for new processors


I am trying to profile L3 cache behaviour for two different architectures, and I encounter a lot of difficulties.

These two architectures are based on X7460 and X7560 Intel Xeon processors.

I am using VTune 9.1 and PTU 4.0 Update 3 to sample the events.

PTU gives me a list of available events for each architecture.

the X7400 series, I have many many events about L1 and L2 caches access
(load, store, self, both_cores, demand, prefetch). Actually, 30% of the
available events are about cache. But NOTHING about L3 cache.

For the X7500 series, I have some LLC (last level cache) events:


and a lot about LLC in OFFCORE_RESPONSE_0 events. But nothing clearly mentionning store or load...

My questions are:

  • are
    the L3 cache events exist? Is it just PTU and VTune which do not know
    where to search, and it is possible to physically interrogate some
    registers? Or L3 caches are too complicated now, and Intel just dropped
    the L3 cache evaluation?
  • what do you use to profile L3 cache events?
  • Since which architecture the L3 are sorely accessible?



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Hi Jerome,

you are right X7460 and X7560 are different architectures.
(X7460 has cores based Intel Core 2 Duo and X7560 is Nehalem based architecture)

Unfortunately neither PTU nor VTune support X7460 any L3 related events for X7460. They deal with core events only while L3 is in uncore.

For Nehalem architecture (so x7500, x5500 series oth.) core events set was extended and there are events telling about about "communication" between core and L3 (which is also uncore). This is why you see those MEM_LOAD_RETIRED.LLC_MISS etc and OFFCORE_RESPONSE.. events.

Sorry this is not helping in your research L3 behaviour for X7460 but at least gives some explanation.

For the explanation of memory events for x7500 series, the document "Performance Analysis on Intel Core i7 and Intel Xeon 5500 processors.pdf" in the PTU root will be helpful.


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