Front End Bound Due To Latency Caused By L1 or i-TLB misses

Front End Bound Due To Latency Caused By L1 or i-TLB misses

TITLE: Front End Bound Due To Latency Caused By L1 or i-TLB misses

ISSUE_NAME: Frontend^FE_latency^L1IorTLB

DESCRIPTION:

Cycles the front end was bound on the latency of L1 I-cache or i-TLB misses

RELEVANCE:

When the back end is requesting uops and the front end cannot deliver them, this can potentially indicate a front end limitation which is affecting performance.  With this metric, this latency is due to either L1 or i-TLB misses.  Applications with large hot code sections tend to run into many issues with the instruction cache and ITLB. This is more typical in server applications.

If ICache misses are causing a significant problem, try to reduce the size of your hot code section, using the profile guided optimizations. Most compilers have options for text reordering which helps reduce the number of pages and, to a lesser extent, the number of pages your application is covering.  If the application makes significant use of macros, try to either convert them to functions, or use intelligent linking to eliminate repeated code.

EXAMPLE:

SOLUTION:

RELATED_SOURCES:

NOTES:

EQUATION:  ICACHE.ICACHE_STALL / CPU_CLK_UNHALTED.THREAD

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