Scaling TSX to multi-socket systems

Scaling TSX to multi-socket systems

Hi,

This is my first time posting here, sorry if this is in the wrong subforum.

To the best of my knowledge, TSX uses the L1 cache coherency protocol to monitor the read/write sets for a transaction. Something which I've been wondering for a while now is how would this scale to systems with >1 processors. I'm not familiar with how such systems maintain cache coherency at L1, but is it feasible for TSX to work correctly and efficiently in these kinds of systems?

Also, is this why the server variants of Haswell are only available for single socket systems?

Thanks,
Stephen

5 posts / 0 nouveau(x)
Dernière contribution
Reportez-vous à notre Notice d'optimisation pour plus d'informations sur les choix et l'optimisation des performances dans les produits logiciels Intel.

Stephen,

Even on a single-socket system, each core has its separate L1 (and L2) cache. In that respect, there is no difference to a multi-socket system. In particular, cache lines are shared or invalidated in L1 cache the same way in both cases, when cores are on the same or on different sockets.

In the past few years, it has always been the case that a new architecture was first released as mobile, desktop, and single-socket servers. Later, processors with the same architecture are released for multi-socket servers. There is nothing unusual about that for the architecture code-named Haswell.

 

Kind regards

Thomas

Thanks for the response, Thomas! That has cleared things up for me.

I'm curious though, is there any delay between when one core performs a write to memory and when the L1 cache of a core on another processor detects it? Is there any potential for a race condition with this?

Stephen,

The other cores are not notified when data is modified. Instead, they need to request the cache line when they want to read or modify it. For this purpose, a cache line can be in one out of four states in the standard MESI protocol:

Modified - The cache line has been modified by the core. A cache line can only enter this state if it was in exclusive state before

Exclusive - Only this core has the cache line. This is required when the core wants to modify this cache line.

Shared - Multiple cores can have the cache line. They can read it but they cannot write it.(They would need to request ownership first for writing.)

Invalid - The cache line is not in the cache.

When a core wants to modify a cache line, the core requests the cache line in exclusive state. The cache line is then evicted from the caches of the other cores . (They become invalid there.) When the core has the cache line in exclusive state, it can modify it (and it becomes "modified").

I hope this helps

Thomas

Ah, there we go, I can see where my confusion was now. I was under the impression that a write could occur when the cache line was shared. There seem to be a lot of diagrams describing MESI online which show the state of a cache line going directly from Shared to Modified after a write has occurred.

Thanks very much for your help Thomas!

Laisser un commentaire

Veuillez ouvrir une session pour ajouter un commentaire. Pas encore membre ? Rejoignez-nous dès aujourd’hui