Zone des développeurs Intel® :
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Juste publié ! Intel® Xeon Phi™ Coprocessor High Performance Programming 
Apprenez les fondements de la programmation pour cette nouvelle architecture et les nouveaux produits. Nouveau !
Intel® System Studio
Intel® System Studio est une suite exhaustive d’outils intégrés de développement de logiciels qui peut accélérer la mise sur le marché, renforcer la fiabilité des systèmes et améliorer l’efficacité énergétique et les performances. Nouveau !
Au cas où vous l’avez manqué – Rediffusion du webinaire en direct de deux jours
Introduction au développement d’applications hautes performances pour processeurs Intel® Xeon® et coprocesseurs Intel® Xeon Phi™.
Structured Parallel Programming
Les auteurs Michael McCool, Arch D. Robison et James Reinders utilisent une approche basée sur des modèles structurés qui devrait rendre le sujet accessible à tous les développeurs de logiciels.

Optimisez les performances de vos applications grâce à la programmation parallèle et avec l'aide des ressources novatrices d'Intel.

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Outils de développement

 

Intel® Parallel Studio

Intel® Parallel Studio, qui apporte aux développeurs Microsoft Visual Studio* C/C++ un traitement parallèle de bout en bout simplifié, fournit des outils avancés permettant d’optimiser les applications clientes pour un traitement multicœur et à nombreux cœurs.

Produits Intel® de développement logiciel ›

Explorez tous les outils qui vous aideront à optimiser vos applications pour l’architecture Intel. Certains outils sont disponibles pour une période d’évaluation gratuite de 45 jours.

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Trouvez des guides et des informations d'assistance sur les outils Intel.

Intel Cluster Ready FAQ: Hardware vendors, system integrators, platform suppliers
Par Werner Krotz-vogel (Intel)Publié le 03/23/20150
Q: Why should we join the Intel® Cluster Ready program? A: By offering certified Intel Cluster Ready systems and certified components, you can give customers greater confidence in deploying and running HPC systems. Participating in the program will help you drive HPC adoption, expand your custom...
Intel Cluster Ready FAQ: Customer benefits
Par Werner Krotz-vogel (Intel)Publié le 03/23/20150
Q: Why should we select a certified Intel Cluster Ready system and registered Intel Cluster Ready applications?A: Choosing certified systems and registered applications gives you the confidence that your cluster will work as it should, right away, so you can boost productivity and start solving n...
Dynamic allocator replacement on OS X* with Intel® TBB
Par Kirill Rogozhin (Intel)Publié le 03/23/20150
The Intel® Threading Building Blocks (Intel® TBB) library provides an alternative way to dynamically allocate memory - Intel TBB scalable allocator (tbbmalloc). Its purpose is to provide better performance and scalability for memory allocation/deallocation operations in multithreaded applications...
Courseware Algorithmic Strategies
Par adminPublié le 02/27/20150
Brute-force algorithms Greedy algorithms Divide-and-conquer Backtracking Branch-and-bound Heuristics Pattern matching and string/text algorithms Numerical approximation algorithms     Parallel Solution to Cat-and-Mouse strategy game problem (Vyukov)     Material Type: Codi...
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Maximum Subarray Problem - Simple Parallelization and Optimizations
Par neshone Publié le 22/12/11 0
Maximum Subarray Problem - Simple Parallelization and OptimizationsUniversity of Novi Sad Faculty of Technical Sciences, Department of Computing and Controlauthors: Predrag Ilkic, Nenad JovanovicDate: October 15th 2011 - November 15th 2011Introduction:This article is an explanation of our m...
Maximum Subarray Problem using TBB and Pipelines
Par ph0b Publié le 16/12/11 0
Algorithm Kadane 2d's classic algorithm has a complexity of O(r²c), where r is the number of rows and c the number of cols. We use it when there is more columns than rows, but instead of tranposing the matrix for the opposite case, we developed a second algorithm that is O(c²r). It's basically a ...
Subarray Problem - A static NUMA-Aware approach
Par krahnack Publié le 24/11/11 3
SubarrayThe subarray problem on a n*m matrix is sequentially solved using an algorithm known as the Kadane 2D algorithm. This algorithm has a O(n²m) complexity. The sequential algorithm is written using 3 loops : for i in (0..n) // <- We parallelize that for j in (i..n...
Introduction aux "Ranges" des TBB
Par megra Publié le 22/11/11 0
Bonjour à tous, Je vais vous présenter une fonctionnalité de la bibliothèque TBB que j'ai eu l'occasion de découvrir durant le concours Acceler8. Pour rappel, TBB qui est l'acronyme de "Threading Building Blocks" est une bibliothèque développée par Intel qui vise à faciliter le parallélisme. Rapp...
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speedup problem using openMP in intel fortran
Par bohluly2
Dear all, I have developed  a program and unfortunately I have speedup problem in it. My program is so big so I have tried to write a sample similar to my program, fortunately this simple program has a same problem with my program.  I need other experiences and your help if it is possible. Thanks, I am using VS2010 and Intel FORTRAN XE 2011 Program:     TYPE var         REAL(8),POINTER :: A, B, C      END TYPE var      REAL(8),POINTER :: A(:), B(:), C(:)      TYPE(var),POINTER  :: vars(:)        TYPE(var),POINTER :: varOMP            REAL*8  t1,t2 ,ai,bi,ci,di,ei,fi        INTEGER(4) c1,c2      INTEGER N, CHUNKSIZE, I, id, f , l      PARAMETER (N=200)      PARAMETER (CHUNKSIZE=10)            Allocate (A(N), B(N), C(N),vars(N)) !     initializations         DO I = 1, N          A(N)      =   I * 1.0          B(N)      =   A(N)          vars(I)%A =>  A(N)          vars(I)%B =>  B(N)          vars(I)%C =>  C(N)          vars(I)%A = 0.51          vars(I)%B...
How can I verify license key?
Par Aleksandr S.1
I have bought few Xeon Phi units. The reseller provided with keys for Intel Parallel Studio. I think they are 6 months demo. However I'd like to know for sure. Is there a way I can check the terms of these keys without activating them, directly with Intel?
Doubts before buy Intel Studio
Par Marcelo C.2
Hi All   I have some doubts regarding the Intel software studio for parallel arch and the Brazilian seller is not able to answer. I need to solve these doubts before buy the Studio for my company. Can somebody help me? 1- Currently we are using OpenMPI. Which advantages Intel MPI provides over OpenMPI? 2- OpenMPI error handling is not good. The MPI Lib from Intel is better for error handling and recovering? For example, if one rank in my mpi comm world dies how can I handle this using Intel lib? 3- Currently we use GCC. Intel compiler is better? We are running in a cluster with several nodes, with MPI doing the communication between the nodes.  Any other recommendations? We host our application at Amazon.  Thank you all in advance!  
Openmp task and parallel construct
Par Patrice l.1
Hi, I am trying to understand the behavior of the Openmp implementation when a parallel do is enclosed in a task. When using nested  the parallel do uses multiple threads. The first question is is that possible to restrict the number of threads to the original thread pool (hardware thread), so that they work on the parallel construct has they become available after completing other task ? (see code below) From reading the forum, i suspect the answer will be no, then what is the best way to combine task and parallel do , inside a task and outside a task. Is it worth it to close the master or single region to do a parallel one, and reopen it right after ? Last question, is there any  becnhmark of using task for a loop instead of a classic parallel do , in both case, fixed work load, and variable work load for each iteration ?   Thanks program omptest use omp_lib implicit none integer :: i !$omp parallel !$omp master print *,'omp get max threads',omp_get_max_thr...
Draining store buffer on other core
Par Boris D.10
Hello, I've a weird question: As I understand, mfence instruction causes draining of the store-buffer on the same core on which it was executed. Is there some way for thread on core A, to cause draining of the store-buffer of core B, without running on core B? Maybe some dirty tricks like simulating IO or exception interrupts?   Thanks!
TBB error : atomic is undefined
Par Aleksandr S.1
I got a C++ code in VS2013 using Intel Compiler XE 15. I write #include "tbb/atomic.h" ...atomic<int> x; I get identifier 'atomic' is undefined. what did I do wrong?
Thread heap allocation in NUMA architecture lead to decrease performance
Par hamed i.4
hi i have server that has 80 logical core (model:dl580g7) .I'm running a single thread per core. each thread doing mkl fft , convolution and many Allocation and DeAllocation from heap with malloc. i previously have server with 16 logical core and there was not a problem and each thread work on its core with 100% cpu usage. when i moved my application from that 16 core server to this 80 core server with numa architecture , after create first thread , that thread works on 100%(kernel time 0%) and With the addition of each thread, performance of other thread decrease so that finally when i have 80 thread cpu usage downgrade to 40% (39% kernel time). because kernel time is increased ,I think the reason for this event is heap sequential mechansim and heap lock. Because of the increasing demand for memory allocation,increased waiting time for each request. i use createheap() on each thread  to eliminate wait for unlock heap memory. but heapalloc can alloc memory up to 512KB. that Insuffic...
A new algorithm of a scalable distributed sequential lock
Par aminer100
Scalable distributed sequential lock Scalable Distributed Sequential lock     Scalable Distributed Sequential lock version 1.11 Author: Amien Moulay Ramdane.  Description: This scalable distributed sequential lock was invented by Amine Moulay Ramdane, and it combines the characteristics of a distributed reader-writer lock with the characteristics of a sequential lock , so it is a clever hybrid reader-writer lock that is more powerful than the the Dmitry Vyukov's distributed reader-writer mutex , cause the Dmitry  Vyukov's distributed reader-writer lock will become slower and slower on the writer side with more and more cores because it transfers too many cache-lines between cores on the writer side, so my invention that is my scalable distributed sequential lock has eliminated this weakness of the Dmitry Vyukov's distributed reader-writer mutex,  so that the writers throughput has become faster and very fast, and my scalable distri...
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