Zone des développeurs Intel® :
Surveillance de plate-forme

Bienvenue dans la communauté Intel de surveillance de plate-forme !

Vous trouverez ici des informations sur la surveillance des performances, le réglage des logiciels et la surveillance de plate-forme. La surveillance des performances recouvre différents sujets, y compris une introduction sur les méthodologies de surveillance et de réglage des logiciels, ainsi que sur les techniques d’optimisation des logiciels et les méthodes les plus connues (BKM, best known methods) pour les utilisateurs novices et expérimentés.

Pour les développeurs, des manuels de référence de programmation sont disponibles avec les dernières informations décrivant l’interface matérielle de la PMU (Performance Monitoring Unit) des microprocesseurs Intel, y compris des ressources de surveillance avec ou sans cœur, ainsi que la source d’informations qui fait autorité sur les événements de performance pouvant être surveillés.

La surveillance de plate-forme comprend des sujets de surveillance d’ordinateurs comme la surveillance du cœur de l’UC et des processeurs graphiques ainsi que d’autres coprocesseurs du système et les mesures et la qualité de service.

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Проблема с intel vmf sdk для windows-7,32b, msvc 2010
Par Belova A.1
Excuse me, but I do'nt understand, why I do'nt see src-folder??? Where are all cpp-files??? I'm explaining: I need installing and building vmf sdk for windows-7, 32 bit, msvc 2010. In specification I hav'nt found install-instructions, but only for samples. Pleas!!! Tell me please, what's wrong??? (excuse me for my english).    В общем, я не могу понять, где исходники? В скаченном пакете только хедеры! 
Monitor whether PCI bus is 33MHz or 66MHz
Par christian f.2
Hi, We have a motherboard with the Intel 6700PXH 64-bit PCI Hub chip. As I understand the chip automatically selects between 33/66/100/133MHz bus rates based on the slowest PCI card installed. Is there a way to monitor/read-out what the selected bus speed is? Thanks! Chris    
Can't run the Intel Power Gadget
Par John D.11
I'm trying to run the Intel Power Gadget on a Win 8.1 x64 system with a Core i7-720QM.  The program and the MS Visual C++ 2010 redistributable library appear to install OK, but the tool will not start.  I try launching it, and nothing happens.  I attached windbg to the executable, but did not learn anything.  I also investigated it with Process Monitor and Dependency Walker, but couldn't get to the bottom of it. The same utility runs fine on a different computer.  Curiously, I might have not installed the MSVC 2012 redistributable on that PC.  I don't see it listed in Programs and Features.  The power gadget runs just fine though. Any ideas?  
Intel® Memory Latency Checker v2 with buffer option
Par Steffen Zeuch4
Hello, the documentation of the Intel Memory Latency Checker states that with the option -bXXX you can specify the buffer size. For example to measure caches instead of DRAM. But this option will not considered for execution. The print message "Using buffer size of" as well as the measures values indicate that it not works. For example mlc --idle_latency –b3000 –c0 –t3 out of the documentation will not work. Is there a workaround?   Kind regards, Steffen
Intel hardware tss (context switch)
Par Jog L.1
Hello, I see the Linux kernel didn't go the hardware route for process switching in ring 0 (kernel). Could one gain a lot by using it ? It is said to be slower than software context switch. Seems strange to me. Any performance pointer ? Thanks
MicroSequencer (MS) @ SNB
Par Mikhail8
Hello, In 64-ia-32-architectures-optimization-manual, chapter B.3.7.2 Understanding the Sources of the Micro-op Queue it is said that UOPs come from DSB, MITE and MS, and a 'typical distribution' is given. It happens so that in the app I'm profiling quite a lot more UOPs are dispatched from MS than suggested as desirable by Intel in the manual while the execution is clearly front-end bound. The problem is, I don't understand why that happens. The manual reads: A large portion of micro-ops coming from the microcode sequencer may be benign, such as complex instructions, or string operations, but can also be due to code assists handling undesired situations like Intel SSE to Intel AVX code transitions. But I am pretty sure there aren't any SSE/AVX instructions employed at all, nor could 'denormals' or string operations occur often enough to produce any notable amount of stirring (the code mainly works with integer values). Is there a complete list of instructions that actually cause M...
Not PMCx reset working when collecting raw PEBS dump
Par jaeyoung j.1
Hello all,   I'm novice on using PEBS facility and I am trying to use "long latency loads" facility and want to dump "raw PEBS records" for further analysis. For writing a simple example, I referenced SDM v3, especially on 18.8.4.1 through 18.8.4.3 (for Sandy Bridge).  When testing, counting long latency loads counter normally works, but PEBS recording does not correctly works.  In the test, I fount that PMCx reset value for adjusting sampling rate does not correctly working, specifically it does not overflow at all for too low counts. According to SDM v3, it needs to trigger overflow to "arm PEBS facility" and to set "PEBS Counter X Reset" for triggering PEBS counters repeatedly.  However, even with set of "PEBS Counter X Reset" in high value (0xFFFFFFFFFF00 in my case), PMCx does not appear to correctly set as preset value in Debug Store Area (0x40H ~ 0x58H), even after first overflow of PMCx. I was trying to find simple examples on this, but it is hard to find the example that in...
Intel PCM, error with very basic code.
Par Jeremie Lagraviere2
Hi everyone, I have a very basic code using IntelPCM: int main(void) { int N = 99999999; PCM * m = PCM::getInstance(); if (m->program() != PCM::Success) { cout << "Intel PCM does not Work"; exit(0); } SystemCounterState before_sstate = getSystemCounterState(); eratosthenesBlockwise(N, 100, 1); SystemCounterState after_sstate = getSystemCounterState(); cout << "Instructions per clock:" << getIPC(before_sstate,after_sstate) << endl; cout << "L3 cache hit ratio:" << getL3CacheHitRatio(before_sstate,after_sstate) << endl; cout << "Bytes read:" << getBytesReadFromMC(before_sstate,after_sstate) << endl; //printf("%d", eratosthenesBlockwise(N, 100, true)); printf("done !"); exit(0); } I compile the code with this command line: g++ -I/home/xxxx/pgashpc/EnergyManagement/IntelPCM/ sie...
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Surveillance des performances des logiciels

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Le 5 janvier 2011, Intel a lancé la 2e génération de processeurs Intel® Core™, anciennement connue sous le nom de code Sandy Bridge, pour PC portables et PC de bureau. Les nouveaux processeurs possèdent une nouvelle architecture révolutionnaire qui associe pour la toute première fois sur la même matrice le « cerveau » de calcul, ou microprocesseur, au moteur graphique. Les nouvelles fonctionnalités comprennent Intel® Insider™, Intel® Quick Sync Video, et une nouvelle version de la technologie Intel® Wireless Display (WiDi) primée, qui ajoute maintenant la résolution 1080p HD et la protection du contenu pour ceux qui souhaitent transmettre du contenu HD de haute qualité de l'écran de leur portable à leur téléviseur.

Restez connecté. Venez nous voir souvent. Nous allons publier les guides de programmation PMU et des outils mis à jour afin de vous fournir les dernières informations sur les innovations de la nouvelle microarchitecture Intel.