124 résultats de recherche pour "software developers guide"

  1. Xeon Phi COREFREQ register


    See Section 5.2 of the document "Intel(R) Xeon Phi(TM) Coprocessor System Software Developers Guide" (go to http://software.intel.com/mic-developer and ...

  2. Communications between MICs and hosts


    Mar 26, 2014 ... MPSS readme and user guide (found in your MPSS installation) ... The Intel® Xeon Phi™ Coprocessor System Software Developers Guide ...

  3. question about caches in mic


    There is a description of this in the System Software Developers Guide (under the Tools & Downloads tab at http://software.intel.com/mic-developer) if you want ...

  4. Accessing Uncore performance counters


    Oct 28, 2012 ... The Intel Arch SW Developer's Guide Volume 3 does list a few ... http://software. intel.com/en-us/comment/1717974#comment-1717974.

  5. Software Controlled Clock Facilities


    Oct 23, 2014 ... How could the duty cycles be software controlled on MIC? ... The guide you mention is a "system" software developer's guide, meaning it is ...

  6. Questions regarding Performance of Hyper threading on Xeon Phi


    See the Intel® Xeon Phi™ System Software Developer's Guide for details. ... exhibit a behavior of software threads migrating amongst logical processors ( pinned ...

  7. Hardware requirements for Xeon Phi Coprocessor hosting system


    To answer my own question, in reading Intel® Xeon Phi™ Coprocessor System Software Developers Guide Page 12: Both x8 and x16 configurations are ...

  8. The Intel Media SDK 2014 is now available for download!


    Also available from the Intel Media Solutions Portal are HEVC software ... Please also refer to the Media SDK Developer Guide for common topics related to ...

  9. Français


    Nov 26, 2014 ... In the User and Reference Guide for the Intel® C++ Compiler 15.0; the the ... the Intel 64 and IA-32 Architectures Software Developer's Manual ...

  10. BIOS writes undocumented bit in MSR 0x3A, need explanation


    Feb 23, 2009 ... In Software Developer's Manual MSR 0x3A bits 7:3 are specified as reserved.In BWG for Core 2 Duo Mobile CPUs those bits are also specified ...

  11. cache eviction policy of Intel newer CPUs


    Take a look at Intel Software Developer Manual for a complete description. ... You can check "The Intel Architecture Software Optimization Guide" chapter 7 for ...

  12. Xeon E5 26xx v3 energy monitor error


    ... (PP0) I always read zero from the MSR_PP0_ENERGY_STATUS. I am using the MSR specification from the Software Developer Manual table 35.25.

  13. Présentation du coprocesseur Intel® Xeon Phi™ | Zone des ...


    Coprocesseur Intel® Xeon Phi™ : Coprocesseur Xeon Phi. Étendez vos capacités matérielles et accroissez votre efficacité tout en optimisant vos économies d' ...

  14. Turbo boost test tool for Haswell CPU


    Dear Sir : Do you have the software tool to check the Turbo boost frequency ... 3 of the Intel Architecture Software Developer's Guide (document 325284-051, ...

  15. Repost: The delay of voltage/frequency scaling


    Oct 20, 2014 ... The document https://software.intel.com/en-us/articles/intel-xeon-phi-coprocessor -system-software-developers-guide discusses about power ...

  16. Preventing Shutdown Due to Overheating


    Please read (from http://www.intel.com/products/processor/manuals/) "Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes 3A and ...

  17. Blogs | Zone des développeurs Intel®


    Our team of software developers, experts, partners and enthusiasts have ... This month we've compiled a list of our most popular IoT stories to guide you through ...

  18. Développeurs Intel AppUp®


    9 mars 2015 ... This paper presents four guidelines that can help guide software developers as they design applications that encourage touch interaction and ...

  19. How does the shutdown on overheating work ?


    Best Reply. Hello Victor, From"Intel 64 and IA-32 Architectures Software Developers Manual Volume 3 (3A & 3B): System Programming Guide" at ...

  20. intel xeon hardware cache events not supported


    25 juil. 2015 ... ... 64 and IA-32 Architectures Software Developers Manual: Volume 3 (3A, 3B, & 3C): System Programming Guide" -- Intel document 325384.

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