The document provides Enhanced Machine Check Architecture Gen 2 (EMCA2) RAS feature’s software (BIOS/Firmware, OS) and hardware integration guidance and validation methodologies which are applied in the Intel® Xeon® Processor E7 – v3 based systems (code named Haswell EX).
The document provides the Memory Address Range Mirroring RAS feature’s software (BIOS/firmware, OS) and hardware integration and validation methodologies which are applied in the Intel® Xeon® Processor E7 – v3 based systems (code named Haswell EX). Integration guides in this document contain Unified Extensible Firmware (UEFI) BIOS and the OS interface setup flows for reporting and configuring mirror memory region during system boot and runtime.
This case study examines the architectural improvements made to the Intel® Xeon® E5 v3 processor family in order to improve the performance of the Galois/Counter Mode of AES block encryption. It looks at the impact of these improvements on the nginx* web server when backed by the OpenSSL* SSL/TLS library. With this new generation of Xeon processors, web servers can obtain significant increases in maximum throughput by switching from AES in CBC mode with HMAC+SHA1 digests to AES-GCM.