performance optimization

Optimize Financial Applications using Intel® Math Kernel Library

Intel® Math Kernel Library (Intel® MKL) contains a wealth of highly optimized math functions that are fundamental to a wide variety of Financial Applications. Intel MKL uses Industry Standard interfaces and can be easily integrated into your current application framework. The Webinar provides an overview of Intel MKL to accelerate financial applications. Topics include:

  • Développeurs
  • Apple OS X*
  • Linux*
  • Microsoft Windows* (XP, Vista, 7)
  • Microsoft Windows* 8.x
  • C/C++
  • Fortran
  • Débutant
  • Intermédiaire
  • Compilateur Intel® C++
  • Compilateur Intel® Fortran
  • Bibliothèque Intel® Math Kernel Library
  • Intel® Parallel Studio XE Composer Edition
  • Learning Lab
  • FSI
  • Financial Services
  • Intel MKL Training
  • performance optimization
  • Outils de développement
  • Secteur des services financiers
  • Optimisation
  • Informatique parallèle
  • Sid Meier’s Civilization* V Finds the Graphics Sweet Spot

    Sid Meier’s Civilization* series has a successful 20-year history. This white paper describes how Firaxis utilized Intel® GPA to ensure Civilization V (Civ5) offers the best possible mix of graphics & game performance for the vast majority of systems.
  • Développeurs
  • Développement de jeu
  • Intel® Threading Building Blocks
  • Intel® INDE
  • Analyseurs de performances graphiques
  • Intel® VTune™ Amplifier
  • Performance analysis
  • performance optimization
  • Civilization
  • sid meier
  • visual computing
  • Firaxis
  • Civ5
  • Task Analyzer
  • Développement de jeu
  • Graphiques
  • Optimisation
  • MEM_TRANS_RETIRED.LOAD_LATENCY events

    There are 8 MEM_TRANS_RETIRED.LOAD_LATENCY_GT_* precise events available on Intel® Microarchitecture Codename Sandy Bridge.  The events allow you to pinpoint loads that exceeded a given latency, measured in CPU clock cycles.  For example, the MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 event is for loads exceeding 4 clocks in latency, and the MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 event is for loads longer than 512 clocks. 

  • Intel® VTune™ Amplifier
  • performance tuning
  • performance optimization
  • performance profiler
  • event-based sampling
  • Optimize Code for the Most-Often Used Code Path


    Challenge

    Overcome the limitation of optimizing compilers in terms of not knowing which code-execution path is most likely to be used. For example, an optimizer can refine a long series of if statements and have it run at great speed; but if it does not know that in the majority of runs, the very last test is the one that is run, the optimizer cannot rearrange the sequence for best possible performance. It has to work on the assumption that all if tests in the sequence are equally probable.

  • Execution
  • performance optimization
  • Informatique parallèle
  • Create Cache-Data Blocks


    Challenge

    Take advantage of data-cache locality with cache-data blocking. Loops with frequent iterations over large data arrays should be restructured such that the large array is subdivided into smaller blocks, or tiles. Each data element in the array is therefore reused within the data block, so that the block of data fits within the data cache, before operating on the next block or tile.

  • Memory cache
  • performance optimization
  • Informatique parallèle
  • S’abonner à performance optimization