Cryptography

Boosting OpenSSL AES Encryption with Intel® IPP

IPP crypto adopts the AES-NI in latest version, which gives users the automatic boost from new silicon without any more work. The article shows the performance gain of OpenSSL AES with IPP AES function.
  • Intel® Parallel Composer
  • Bibliothèque Intel® Integrated Performance Primitives (IPP)
  • AES
  • encryption
  • IPP Cryptography Library
  • Westmere
  • Cryptography
  • OpenSSL
  • IPP Cryptography
  • IPP cpu optimization
  • openssl-ipp
  • AES-NI
  • decryption
  • Optimisation
  • Boosting Cryptography Performance with Intel® Libraries

    by Muneesh Nagpal, Gururaj Nagendra, and Alexey Omelchenko


    Introduction

    This simple optimization walk-through improves an already-optimized sample OpenSSL application's performance by 35% using Intel® cryptography library functions.

  • Développeurs
  • Intel Performance Libraries
  • Cryptography
  • An Intel hardware based digital random number technology could mitigate recent RSA security flaw

    Mathematicians from Europe and the United States are reporting a flaw in the RSA encryption method that apparently hinges on crypto keys being created with insufficient randomness.

    AES-NI in Laymen's Terms

    What is AES-NI - first answer
    AES-NI are a set of six new instructions introduced by Intel when we introduced the new 2010 Intel® Core™ processor family code named Westmere. AES-NI stands for Advanced Encryption Standard - New Instructions. These instructions implement hardware accelerated versions of certain compute intensive steps used in the AES (RijnDael) algorithm.

    Okay - so what is the Advanced Encryption Standard (AES)?

    Want a faster calculated hash and a block cipher? “Stitch” them!

    Hello.

    We just released the very interesting paper showing the way to speed up a pair of independent functions or algorithms, like a block cipher and a hash often called sequentially on the same input buffer.

    One can greatly improve the utilization of the underlying microarchitecture’s execution resources by combining two algorithms and computing them together at the same time, we call it “stitching”.

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