timing

Measuring performance in HPC

This is the first article in a series of articles about High Performance Computing with the Intel Xeon Phi. The Intel Xeon Phi is the first commercial product of Intel to incorporate the Many Integrated Core architecture. In this article I will present the basics of the Xeon Phi architecture, the programming models and what we can do to measure the performance in cycles for micro benchmarks.

  • Développeurs
  • Professeurs
  • Étudiants
  • Linux*
  • C/C++
  • Intermédiaire
  • Compilateur Intel® C++
  • Compilateur Intel® C++ et bibliothèque de performance pour QNX* Neutrino* RTOS
  • Intel® C++ Composer XE
  • Intel® Cilk™ Plus
  • Intel® Composer XE
  • Bibliothèque Intel® Math Kernel Library
  • OpenMP*
  • MIC
  • Xeon
  • Phi
  • performance
  • timing
  • offload
  • native
  • Débogage
  • Intel® Many Integrated Core Architecture
  • Optimisation
  • Informatique parallèle
  • Parallélisation
  • Vectorisation
  • S’abonner à timing