Intel® Xeon Phi™ Coprocessor

使用英特尔® 软件开发仿真器(英特尔® SDE)计算 “FLOP”

目的

作为分析指标和/或基于性能指标评测目的,浮点运算 (FLOP) 速度广泛运用于高性能计算 (HPC) 社区。 许多 HPC 贡献者(比如戈登·贝尔)要求提交应用时注明 FLOP 速度。

本文所述的方法不依赖于性能监控单元 (PMU) 事件/计数器。 它是一种使用英特尔® SDE 评估 FLOP 的替代性软件方法。

  • Développeurs
  • Professeurs
  • Étudiants
  • Linux*
  • Serveur
  • Avancé
  • Intermédiaire
  • Intel® Software Development Emulator
  • FLOP
  • Knight’s Landing
  • Intel® SDE
  • HPC
  • Floating point operations
  • Intel® Xeon Phi™ Coprocessor
  • Intel® Core™ processor family
  • Intel® Many Integrated Core Architecture
  • Explicit offload for Quantum ESPRESSO

    Purpose

    This code recipe describes how to get, build, and use the Quantum ESPRESSO code that includes support for the Intel® Xeon Phi™ coprocessor with Intel® Many-Integrated Core (MIC) architecture. This recipe focuses on how to run this code using explicit offload.

  • Développeurs
  • Linux*
  • Serveur
  • Intermédiaire
  • Bibliothèque Intel® MPI Library
  • Quantum ESPRESSO
  • Intel® Xeon Phi™ Coprocessor
  • Intel® Many Integrated Core Architecture
  • Calculating “FLOP” using Intel® Software Development Emulator (Intel® SDE)

    Purpose

    Floating point operations (FLOP) rate is used widely by the High Performance Computing (HPC) community as a metric for analysis and/or benchmarking purposes. Many HPC nominations (e.g., Gordon Bell) require the FLOP rate be specified for their application submissions.

    The methodology described here DOES NOT rely on the Performance Monitoring Unit (PMU) events/counters. This is an alternative software methodology to evaluate FLOP using the Intel® SDE.

  • Développeurs
  • Professeurs
  • Étudiants
  • Linux*
  • Serveur
  • Avancé
  • Intermédiaire
  • Intel® Software Development Emulator
  • FLOP
  • Knight’s Landing
  • Intel® SDE
  • HPC
  • Floating point operations
  • Intel® Xeon Phi™ Coprocessor
  • Intel® Core™ processor family
  • Intel® Many Integrated Core Architecture
  • LAMMPS* for Intel® Xeon Phi™ Coprocessor

    Purpose

    This code recipe describes how to get, build, and use the LAMMPS* code for the Intel® Xeon Phi™ coprocessor.

    Introduction

    Large-scale Atomic/Molecular Massively Parallel Simulator (LAMMPS*) is a classical molecular dynamics code. LAMMPS has potentials for solid-state materials (metals, semiconductors), soft matter (biomolecules, polymers), and coarse-grained or mesoscopic systems. LAMMPS can be used to model atoms, or, more generically, as a parallel particle simulator at the atomic, meso, or continuum scale.

  • Serveur
  • LAMMPS*
  • Intel® Xeon Phi™ Coprocessor
  • molecular dynamics
  • Intel® Many Integrated Core Architecture
  • System Administration for the Intel® Xeon Phi™ Coprocessor

    Updated December 12 2014

    Preface


    This document provides a general overview of system administration on the Intel® Xeon Phi™ coprocessor. It is written with the small scale system administrator in mind. It is not intended as a replacement for the documentation which comes with each release of the Intel® Many Integrated Core Architecture (Intel® MPSS) but as a supplement, providing advice, troubleshooting suggestions and pointers to other useful documents.

  • Développeurs
  • Serveur
  • MIC
  • Intel® Xeon Phi™ Coprocessor
  • Intel® Xeon Phi™ Coprocessor System Admistration Guide
  • S’abonner à Intel® Xeon Phi™ Coprocessor