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ADVANCED COMPUTER CONCEPTS FOR THE (NOT SO) COMMON CHEF: INTRODUCTION

 

TITLE:
INTRODUCTION
ADVANCED COMPUTER CONCEPTS FOR THE (NOT SO) COMMON CHEF

While talking to a very intelligent but non-engineer colleague, I found myself needing to explain the threading and other components of the Intel® Xeon Phi™ ⅹ100 and ⅹ200 architectures. The first topic that came up was hyper-threading, and more specifically, the coprocessor’s version of hyper-threading. Wracking my brain, I finally hit upon an analogy that seemed to suit: the common kitchen.

Special Promotion for ANSYS Developers: Intel® Xeon Phi™ Coprocessors

Special Promotion for ANSYS Developers: Intel® Xeon Phi™ Coprocessors

 

ANSYS* and Intel worked closely together to deliver up to 2.2x (1) higher performance, for ANSYS Mechanical* R16.0,  by optimizing the application code for the multi-core Intel® Xeon® processor E5-2600 v2 and v3 families and the many-core Intel® Xeon Phi™ coprocessor. The combination offers tremendous performance potential for structural mechanics simulations, at relatively low cost and without altering the end-user experience or complicating the IT environment.

  • Développeurs
  • ANSYS
  • MIC
  • Intel Xeon Phi Coprocessor
  • BLAST for the Intel® Xeon Phi™ Coprocessor

    Purpose

    This code recipe describes how to get, build, and use the BLAST+ code that includes support for the Intel® Xeon Phi™ coprocessor with Intel® Many-Integrated Core (MIC) architecture.

  • Développeurs
  • Linux*
  • Serveur
  • Intermédiaire
  • Intel(R) Xeon Phi(TM) Coprocessor
  • BLAST
  • MIC
  • Intel(R) Xeon(R) processors
  • Bioinformatics
  • Intel® Many Integrated Core Architecture
  • System Administration for the Intel® Xeon Phi™ Coprocessor

    Updated December 12 2014

    Preface


    This document provides a general overview of system administration on the Intel® Xeon Phi™ coprocessor. It is written with the small scale system administrator in mind. It is not intended as a replacement for the documentation which comes with each release of the Intel® Many Integrated Core Architecture (Intel® MPSS) but as a supplement, providing advice, troubleshooting suggestions and pointers to other useful documents.

  • Développeurs
  • Serveur
  • MIC
  • Intel® Xeon Phi™ Coprocessor
  • Intel® Xeon Phi™ Coprocessor System Admistration Guide
  • Intel® MPSS - changes in release cadence and support

    Up until now, Intel has been releasing its Manycore Platform Software Stack (Intel® MPSS) on a quarterly cadence, with each release being supported for 1 year from the date it was issued.

    Beginning October 2014, the release timing and the support lifetime of Intel® MPSS is changing, namely to support divergent community needs:

    Intel® Xeon Phi™ Coprocessor – Applications and Solutions Catalog

     

    The PDF document attached to this article contains a growing list of available, downloadable or work-in-progress code that can be run, or actively being optimized to run on Intel® Xeon Phi™ Coprocessors. 

  • Xeon Phi
  • Intel Xeon Phi Coprocessor
  • Knights Corner
  • Knights Landing
  • MIC
  • High performance computing
  • HPC
  • HPC applications
  • Parallel Programming
  • sample code
  • application modernization
  • application optimization
  • Intel® Many Integrated Core Architecture
  • S’abonner à MIC