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Xeon Phi refuses Putty log in

Hi, I am trying to log into a Xeon Phi 3120A for the first time using Putty, but the log-in is refused and the connection asks for a password. What I am doing is: 1. Create public and private keys in puttygen (SSH2-RSA 1024 bit) 2. Register the public keys with the Xeon Phi with micctrl --addssh root -f "C:\Program Files\Intel\MPSS\bin\authorized_keys" It says: root: Updated with authorized key 3. micctrl --stop and then --start 4. Start putty and log into root@192.168.1.100 with SSH auth set to use the private keys saved in a ppk file.

Screen resolution ( 1366x768 ) stretch in Windows XP service pack 3

Hi,

I am using Intel D101GGC Mother board with 1 GB RAM and Windows XP Service pack 3.

I replaced my CRT monitor to Samsung 18.5 inch LED - LS19B150BS-XL Monitor, I am facing the screen stretched when i changed the resolution to 1366 x 768. 

If i changed to 1280 x720, i faced flickering issue

Please suggest me how can avoid  this issue, I need to upgrade my mother board or my Operating system 

Please guide me..

my code takes lot of time to execute and returns incorrect result

Hello, 

I am new to programming with MIC cards. I am trying to run a very simple program but it appears that it is taking a long time to offload the data over to the MIC card and also the final output seems to be incorrect, can anyone help me figure out my mistake, please. 

#include <iostream>
#include <memory>
#include "omp.h"
#include <malloc.h>

using namespace std; 

Problems installing MPSS 3.1.2

I am attempting to install MPSS 3.1.2 on a cluster of four CentOS 6.5 boxes.  Node 1 installed fine (as per the instructions from the provided readme).  However the other three nodes are having strange issues.  The previous version of mpss was unloaded and uninstalled as per the instructions and the files located in the ...RHEL-6.5.tar were installed with yum.  However the mpss service does not start and module mic.ko will not load:

modprobe mic
FATAL: Module mic not found.

about IA64 architecture?

Hi,

I have Intel Pentium Dual-Core CPU, and when I lunched the Intel Processor Identification Utility I got "Intel(R) 64 Architecture: Yes",

here is the screenshot:

<a href="http://picsee.net" target="_blank"><img src="http://picsee.net/upload/2014-01-12/04b79f4a05e1.png"></a>

really this appears strange to me, since the CPU is an Intel Pentium that is not Itanium,

so is that true that my cpu has IA64 architecture or no? thanks.

 

Intel MIC with OFED

Hi,

 

I am trying to build hpc cluster with 4 phi card and 2 nodes.

i am using mlx interconnect for mpi communication.

 

th cluster details given below:

centos 6.4, intel cluster 2013, MPSS 3.1.2,OFED 1.5.4.1

Intel Phi card is configured with external network connection on bridge with eth0 interface

opensmd,mpss,openibd,ofed-mic services are running properly.

Only on all 4  intel phi card is used for running service program

Question:-

MIC General purpose register to vector register move

Is there any way of moving data from general purpose register to MIC vector register without going through memory?

By the way, xeon phi system software development guide says there is an VABSDIFPI instruction,  but there seems to be no intrinsics posted in ICC compiler reference.   So which is correct?

 

 

Fast Panorama Stitching

 

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Introduction

Taking panoramic pictures has become a common scenario and is included in most smartphones’ and tablets’ native camera applications. Panorama stitching applications work by taking multiple images, algorithmically matching features between images, and then blending them together. Most manufacturers use their own internal methods for stitching that are very fast. There are also a few open source alternatives.

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  • basic cache parameters in table, discrepancies in descriptions

    I would like to clarify the basic cache parameters in "Intel Xeon Phi Coprocessor System Software Developers Guide".

    In Table 2.4 "Cache Hierarchy", the table says duty cycles of L2 is "1 per clock", but the text body says "The L1 cache can be accessed each clock, whereas the L2 can only be accessed every other clock". It may mean the duty cycles is 2 clocks.

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