Intel® Many Integrated Core Architecture

How many bytes of instructions removed from LI Cache

Hi, I have an assignment for my computer architecture class. 

I have read intel's Architecture Optimization Manual and still cannot find the answer.I need to know how many bytes of Instructions are removed from the L1 instruction  cache.

Say I run a FFT sequence/pr, it is of say X bytes.

1.Are X bytes, cached as whole in the L1 cache or it is partially cached?

2. Are the X bytes fully(wholly) transmitted to the L2 cache? 

3. Does the same procedure 1 and 2, hold, when FFT program/Sequence is removed?

Xeon Phi: Memory leak?


I write a rpc-like application to run on Xeon Phi and dynamic link with MKL. However after the program finish (exit), the memory on micsmc is still high, for example, at one of the Xeon Phi nodes the memory usage is of 1172MB.  Howver if I reboot the Xeon Phi, the memory usage after reboot would be of 418MB.  It seems to me that the system has leaking memory problem. How can I recover the memory lost without rebooting Xeon Phi?  Thanks,



Linking C++ and Fortran objects

Platform: CentOS release 6.6 (Final)

GCC: 4.9.1

Intel Parallel Studio Cluster Edition 2016

I am working on a bioinformatics application that my team and I have successfully compiled for Intel Xeon processor. Now we're trying to compile the application for MIC but we have a hard time linking it. The error that we get is the following:

x86_64-k1om-linux-ld: cannot find -lstadc++
/opt/mpss/3.2.1/sysroots/x86_64-mpsssdk-linux/lib/ could not read symbols: File in wrong format

MPSS 3.6 is available


Please note that the new MPSS 3.6 is available at

MPSS 3.6 will be supported until the end of March 2016. Major changes in MPSS 3.6 include:

  • hStreams Beta

  • k1om gcc update from 4.7.0 experimental to 5.1

  • k1om glibc update to 2.21

  • MLNX_OFED 2.4 support

  • RHEL 6.4 support drop

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