Intel® Many Integrated Core Architecture

What is Code Modernization?

Modern high performance computers are built with a combination of resources including: multi-core processors, many core processors, large caches, high speed memory, high bandwidth inter-processor communications fabric, and high speed I/O capabilities. High performance software needs to be designed to take full advantage of these wealth of resources.

  • Développeurs
  • Serveur
  • Interface de transmission de messages
  • Modernisation du code
  • Intel® Many Integrated Core Architecture
  • Informatique parallèle
  • Parallélisation
  • Vectorisation
  • 什么是代码现代化?

    现代高性能计算机由下列资源组合构建而成:多核处理器众核处理器、大型高速缓存,高带宽进程间通信结构和高速 I/O 功能。 高性能软件需经过设计,以充分利用这些丰富的资源。 无论是重新构建并/或调优现有应用以发挥最高性能,或为现有或未来设备构建新应用,了解编程模型和高效利用资源之间的相互作用极其关键。 以此为起点,全面了解代码现代化。 关于性能,您的代码至关重要!

  • Développeurs
  • Serveur
  • Interface de transmission de messages
  • Modernisation du code
  • Intel® Many Integrated Core Architecture
  • Informatique parallèle
  • Parallélisation
  • Vectorisation
  • Optimization Techniques for the Intel® MIC Architecture: Part 2 of 3

    Abstract

    This is part 2 of a 3-part educational series of publications introducing select topics on optimization of applications for Intel’s multi-core and manycore architectures (Intel® Xeon®  processors and Intel® Xeon Phi™ coprocessors).

    In this paper we discuss data parallelism. Our focus is automatic vectorization and exposing vectorization opportunities to the compiler. For a practical illustration, we construct and optimize a micro-kernel for particle binning particles.

  • Développeurs
  • Professeurs
  • Étudiants
  • Linux*
  • C/C++
  • Modernisation du code
  • Intel® Many Integrated Core Architecture
  • Vectorisation
  • Xeon Phi crashes on too-large SCIF memory registration

    Is there a mechanism with SCIF to register a memory region with all endpoints? At the moment, I have a for-loop with scif_register() on this memory region with each endpoint. Memory registration is rather expensive and I would like to avoid unnecessarily incurring this cost repeatedly if there is possibly a faster way to register with all endpoints.

    With my current method, if the memory region is sufficiently large (e.g., 6 GB+), the coprocessor crashes during scif_register():

    Force xeon level precision on Xeon phi or vice versa

    Hi all,

    I have been running a program where precision of doubles mean a lot to my program.

    However due to some strange reason it seems like Xeon phi is rounding off a few bits(at 10^-8th bit) and this seems to be causing some instabilities to my model. A small round off error grows over my model over iteration of time step and my model fails to converge.

    here is  some sample differences in error.

    Xeon phi value

    Coprocesador Intel® Xeon Phi™: catálogo de aplicaciones y soluciones

     

    El documento PDF que se adjunta a este artículo contiene una lista, en constante aumento, de código disponible, descargable o en elaboración que se puede ejecutar en coprocesadores Intel® Xeon Phi™ o que está siendo optimizado para ejecutarse en ellos.


  • Xeon Phi
  • Intel Xeon Phi Coprocessor
  • Knights Corner
  • Knights Landing
  • MIC
  • High performance computing
  • HPC
  • HPC applications
  • Parallel Programming
  • sample code
  • application modernization
  • application optimization
  • Intel® Many Integrated Core Architecture
  • S’abonner à Intel® Many Integrated Core Architecture