Intel ISA Extensions

We need standardization of the x86 instruction set

The evolution of the x86 instruction set is completely chaotic. Intel and AMD are competing to make new instructions for the same purpose and the result is incompatibility. For example, the virtualization instructions are not compatible.
We need a transparent decision process and an open standardization of new instruction codes. Please see my analysis at
What is your opinion? Comments are welcome.

Illegal Instruction -- Intel SDE with AES instructions

Hello, having a problem with the emulator giving me an Illegal Instruction exception when I run a program that use the AES intrinisics. I compiled it with the latest icpc version, running on Ubuntu 9.10. I'm used the same code and emulator under Ubuntu 9.04, and it was working/running. Any ideas as to what I can do it get it working, or at least point me out in a debugging direction to see how I could...



How does address be mapped onto a memory bank

Hi, all!

I want to do some test and I have tofigure outwhichaddress will bemapped onto which memory bank?To my understanding, I have toknow that, inone address, which bits represent bank No, which bits represent row, which bits represent column. Now, I am using Core 2 processor and could know the information about my memory chips, but can't find the address matching relation between them.

Please give me some help or any literatures I could refer to.

Many thanks!

TSC Problem


I have a strange situation on my systems with Intel Celeron M 600MHz processor.

In my routine I must calculate the elapsed time between an operation and another.


LARGE_INTEGER ini, fin, delta;






I Use my RDTSC function for calculate delta time:

__inline __int64 RDTSC()



__asm {

push eax

push edx

PTEST improvement?


another benchmark: while I was testing compare performance, the next step is to compare branching on compares, so I wanted to show the impact of ptest in comparison to pmovmskb - cmp. But my results show that ptest is slower in almost all cases. See the first page of compare.pdf for the results. I would understand ptest and pmovmskb showing the same speed if both instructions count as being in the "integer domain", therefore both having the same 1 cycle penalty wrt. domain crossing (is this correct?).

Low rate on sse2 code

why this scalar sse2 code (all data in L1 cache) executes on Core2 only on rate 1.49 flop/cycle?

movsd(%esi), %xmm5
movsd(%ebx), %xmm4
addl$4, %edi
mulsd%xmm5, %xmm4
addsd%xmm4, %xmm3
movsd(%ecx), %xmm4
mulsd%xmm5, %xmm4
addsd%xmm4, %xmm2
movsd(%edx), %xmm4
mulsd%xmm5, %xmm4
addsd%xmm4, %xmm1
movsd(%eax), %xmm4
mulsd%xmm5, %xmm4
movsd8(%esi), %xmm5
addsd%xmm4, %xmm0

Could intel somehow initiate migration/cleanup for x86 instruction set?

I don't like x86 instruction set because it is full of exceptions and arbitrary historical conventions. On top of this every new group of instructions follows the suit. It's not CISC anymore, more like OCISC standing for 'Over-Complicated Instruction Set Computer'.

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